MC68HC908QY4CDW Freescale Semiconductor, MC68HC908QY4CDW Datasheet - Page 144

• Manufacturer Part Number: MC68HC908QY4CDW
• Description: IC MCU 4K FLASH W/ADC 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908QY4CDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Connectivity: -

Development Support
15.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
15.3.1.5 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
15.3.1.6 Baud Rate
The monitor communication baud rate is controlled by the frequency of the external or internal oscillator
and the state of the appropriate pins as shown in
Table 15-1
bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in
forced monitor mode, the effective baud rate is the bus frequency divided by 335.
15.3.1.7 Commands
The monitor ROM firmware uses these commands:
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•
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READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the
User
Monitor
Modes
START
BIT
Vector High
0
$FFFE
$FEFE
Reset
BIT 0
1
2
BIT 1
MISSING STOP BIT
3
MC68HC908QY/QT Family Data Sheet, Rev. 6
Vector Low
Figure 15-13. Monitor Data Format
Figure 15-14. Break Transaction
$FFFF
$FEFF
4
Reset
BIT 2
Table 15-2. Mode Difference
5
6
BIT 3
Vector High
7
$FEFC
$FFFC
Break
BIT 4
Table
Functions
BIT 5
15-1.
Vector Low
2-STOP BIT DELAY BEFORE ZERO ECHO
$FFFD
$FEFD
Break
BIT 6
0
1
BIT 7
2
Vector High
$FEFC
$FFFC
3
STOP
SWI
BIT
4
START
NEXT
5
BIT
6
Vector Low
Freescale Semiconductor
$FFFD
$FEFD
SWI
7