MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 118
MCF5307FT90B
Manufacturer Part Number
MCF5307FT90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Set 0
Set 127
Cache Operation
4-20
After reset, the cache is
invalidated, ways 0 and 1
are then written with data
that should not be
deallocated.
A:Ways 0 and 1 are filled.
Way 0 Way 1 Way 2 Way 3
Ways 2 and 3 are
invalid.
Invalid (V = 0)
Valid, not modified (V = 1, M = 0)
Valid, modified (V = 1, M = 1)
Freescale Semiconductor, Inc.
For More Information On This Product,
B:CACR[DHLCK] is set,
After CACR[HLCK] is
set, subsequent cache
accesses go to ways 2
and 3.
Way 0 Way 1 Way 2 Way 3
locking ways 0 and 1.
Figure 4-7. Cache Locking
Go to: www.freescale.com
MCF5307 User’s Manual
C:When a set in Way 2 is
While the cache is
locked and after a
position in ways is full,
the set in Way 3 is
updated.
Way 0 Way 1 Way 2 Way 3
occupied, the set in way 3
is used for a cacheable
access.
D:Write hits to ways 0
While the cache is
locked, ways 0 and 1 can
be updated by write hits.
In this example, memory
is configured as
copyback, so updated
cache lines are marked
modified.
Way 0 Way 1 Way 2 Way 3
and 1 update cache
lines.
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