MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 376
MCF5307FT90B
Manufacturer Part Number
MCF5307FT90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Interrupt Control Signals
17.3 Interrupt Control Signals
The interrupt control signals supply the external interrupt level to the MCF5307 device.
17.3.1 Interrupt Request (IRQ1/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4,
The IRQ1, IRQ3, IRQ5, and IRQ7 signals are the default interrupt request signals (IRQn).
However, by setting the appropriate bit in the interrupt port assignment register (IRQPAR),
IRQ1, IRQ3, and IRQ5 can be changed to function as IRQ2, IRQ6, and IRQ4, respectively.
See Section 9.2.4, “Interrupt Port Assignment Register (IRQPAR).”
17.4 Bus Arbitration Signals
The bus arbitration signals provide the external bus arbitration control for the MCF5307.
17.4.1 Bus Request (BR)
The BR output indicates to an external arbiter that the processor is requesting to be bus
master for one or more bus cycles. BR is negated when the MCF5307 begins an access to
the external bus with no other internal accesses pending. BR remains negated until another
internal request occurs.
17.4.2 Bus Grant (BG)
An external arbiter asserts the BG input to indicate that the MCF5307 can take control of
the bus on the next rising edge of BCLKO. When the arbiter negates BG, the MCF5307 will
release the bus as soon as the current transfer completes. The external arbiter must not grant
the bus to any other master until both BD and BG are negated.
17-12
Table 17-10. TM[2:0] Encodings for TT = 11 (Interrupt Level) (Continued)
and IRQ7)
Freescale Semiconductor, Inc.
For More Information On This Product,
TM[2:0]
010
011
100
101
110
111
Go to: www.freescale.com
MCF5307 User’s Manual
Interrupt level 2 acknowledge
Interrupt level 3 acknowledge
Interrupt level 4 acknowledge
Interrupt level 5 acknowledge
Interrupt level 6 acknowledge
Interrupt level 7 acknowledge
Transfer Modifier
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