MC68HC908JB12DW Freescale Semiconductor, MC68HC908JB12DW Datasheet
MC68HC908JB12DW
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MC68HC908JB12DW Summary of contents
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MC68HC908JB16 Technical Data M68HC08 Microcontrollers Rev. 1.1 MC68HC908JB16/D August 1, 2005 freescale.com ...
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... Freescale was negligent regarding the design or manufacture of the part. Freescale, Inc Equal Opportunity/Affirmative Action Employer. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor © Freescale, Inc., 2002 Technical Data 3 ...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision Date Level May 1 First general release. 2002 Technical Data 4 Revision History Description Page Number(s) — MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... Section 17. Computer Operating Properly (COP 297 Section 18. Low-Voltage Inhibit (LVI 303 Section 19. Break Module (BRK 307 Section 20. Electrical Specifications . . . . . . . . . . . . . . . . . . 315 Section 21. Mechanical Specifications . . . . . . . . . . . . . . . . 325 Section 22. Ordering Information 329 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Module (SCI 207 List of Sections List of Sections Technical Data 5 ...
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... List of Sections Technical Data 6 MC68HC908JB16 List of Sections Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Power Supply Pins (V DD Voltage Regulator Output Pin (V Oscillator Pins (OSC1 and OSC2 External Reset Pin (RST External Interrupt Pins (IRQ, PTE4/D– ...
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... FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 62 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 63 FLASH Program Operation .64 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 66 ROM-Resident Routines Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Section 5. Configuration Register (CONFIG) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Table of Contents MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Section 6. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Wait Mode ...
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... Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SWI Instruction 112 Interrupt Status Registers 112 Interrupt Status Register 112 Interrupt Status Register 114 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 114 Table of Contents MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 SIM Break Status Register (SBSR 118 SIM Reset Status Register (SRSR 119 SIM Break Flag Control Register (SBFCR 120 Section 9 ...
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... Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Address Field (ADDR 172 Endpoint Field (ENDP 172 Cyclic Redundancy Check (CRC 172 End-of-Packet (EOP .172 Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table of Contents MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... USB Endpoint 2 Data Registers . . . . . . . . . . . . . . . . . . . . . 200 11.9 11.9.1 11.9.1.1 11.9.1.2 11.9.1.3 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . . 175 USB Reset Signalling .175 Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Voltage Regulator ...
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... Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .222 Receiver Wakeup 225 Receiver Interrupts 226 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 SCI During Break Module Interrupts .228 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Table of Contents MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor TxD (Transmit Data 228 RxD (Receive Data 228 I/O Registers 229 SCI Control Register 229 SCI Control Register 232 SCI Control Register 235 SCI Status Register 238 SCI Status Register 242 SCI Data Register ...
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... Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Data Direction Register 273 Port 275 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Data Direction Register 277 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . .279 Section 15. External Interrupt (IRQ) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Table of Contents MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 PTE4/D– Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 285 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 286 IRQ Option Control Register 287 Section 16. Keyboard Interrupt Module (KBI) Contents ...
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... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 Low V Detector 304 DD Low V Detector 305 REG LVI Control and Configuration . . . . . . . . . . . . . . . . . . . . . . . . 305 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 Section 19. Break Module (BRK) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Table of Contents MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 20.13 CGM Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 322 20.14 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . 324 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 310 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .310 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 310 COP During Break Interrupts ...
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... Technical Data 20 Section 21. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 32-Pin Low-Profile Quad Flat Pack (LQFP 326 28-Pin Small Outline Integrated Circuit (SOIC 327 Section 22. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Table of Contents MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Title MC68HC908JB16 MCU Block Diagram . . . . . . . . . . . . . . . . . . 32 32-Pin LQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 33 28-Pin SOIC Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Regulator Supply Capacitor Configuration . . . . . . . . . . . . . . . . 35 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .44 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 60 FLASH Control Register (FLCR) ...
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... Monitor Mode Circuit 125 Low-Voltage Monitor Mode Entry Flowchart 127 Monitor Data Format 129 Break Transaction .129 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . . 134 Monitor Mode Entry Timing .135 List of Figures Page MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... USB Endpoint 0 Data Registers (UE0D0–UE0D7 198 11-27 USB Endpoint 1 Data Registers (UE1D0–UE1D7 199 11-28 USB Endpoint 2 Data Registers (UE2D0–UE2D7 200 11-29 OUT Token Data Flow for Receive Endpoint 202 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Title List of Figures List of Figures Page Technical Data 23 ...
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... PLL2 N Divider Select Register Low (PNSL2 258 13-12 PLL1 R Divider Select Register Low (PRSL1 259 13-13 PLL2 R Divider Select Register Low (PRSL2 259 13-14 Phase Detector Control Register (PDCR 260 Technical Data 24 Title MC68HC908JB16 List of Figures Page Rev. 1.1 — Freescale Semiconductor ...
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... Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 309 19-2 Break Module I/O Register Summary . . . . . . . . . . . . . . . . . . . 309 19-3 Break Status and Control Register (BRKSCR 311 19-4 Break Address Register High (BRKH 312 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Title List of Figures List of Figures Page Technical Data 25 ...
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... Break Address Register Low (BRKL 312 19-6 SIM Break Status Register (SBSR 313 19-7 SIM Break Flag Control Register (SBFCR 314 21-1 32-Pin LQFP (Case #873A 326 21-2 28-Pin SOIC (Case #751F .327 Technical Data 26 Title MC68HC908JB16 List of Figures Page Rev. 1.1 — Freescale Semiconductor ...
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... Monitor Mode Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Title Summary of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 ROM-Resident Routines Summary of FLASH Routine Variables . . . . . . . . . . . . . . . . . . 68 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SIM Module Signal Name Conventions ...
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... Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 14-3 Port C Pin Functions 271 14-4 Port D Pin Functions 274 14-5 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 16-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 22-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Technical Data 28 Title MC68HC908JB16 List of Tables Page Rev. 1.1 — Freescale Semiconductor ...
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... The MC68HC908JB16 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 ...
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... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 30 (with USB module disabled) (32-pin package pins and 10mA direct drive for normal LED on 4 pins (28-pin package) General Description 1 feature MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... MCU Block Diagram Figure 1-1 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Serial communications interface module (SCI) Dual clock generator modules (CGM) (32-pin package) In-circuit programming capability using USB communication or standard serial link on PTA0 pin System protection features: – Optional computer operating properly (COP) reset – ...
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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH MEMORY — 16,384 BYTES USER RAM — 384 BYTES MONITOR ROM — 1,472 BYTES USER FLASH VECTORS — 48 BYTES (1) OSC1 OSCILLATOR (1) ...
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... OSC1 OSC2 VREG VDD PTD0 PTD1 PTD2 PTD3 PTD4 PTE1/T1CH01 PTE3/D+ PTE4/D– PTC0/TxD Figure 1-3. 28-Pin SOIC Pin Assignment MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor VSSA1 24 CGMOUT2 23 22 PTA0/KBA0 PTA1/KBA1 21 20 PTA2/KBA2 PTA3/KBA3 19 PTE0/TCLK 18 PTE2/T2CH01 17 Pins not available on 32-pin package: ...
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... BULK V DD NOTE: Values shown are typical values. Figure 1-4. Power Supply Bypassing ) REG pin requires an external bulk capacitor 4.7µF REG General Description Figure 1-4 . BYPASS used REG Figure 1-5 shows. pin as possible. REG MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... External Interrupt Pins (IRQ, PTE4/D–) IRQ is an asynchronous external interrupt pin. IRQ is also the pin to enter Monitor mode. The IRQ pin contains a software configurable pullup device to V (See MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor V REG V REG Figure 1-5. Regulator Supply Capacitor Configuration . (See DD (SIM).) . PTE4/D– ...
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... Options.) Each pin can also be programmed (KBI).) General Description are the ground pins for SSA1 . Connect V and V DD SSA0 SSA1 . Decoupling of these pins SS directly to REGA1 . REGA0 Ports.) Each pin contains a when the pin is configured as DD Section 16. Keyboard MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... Any unused inputs and I/O ports should be tied to an appropriate logic level (either V do not require termination, termination is recommended to reduce the possibility of static damage. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Section 14. Input/Output (I/O) 14.7 Port Options.) when the pin is configured as an input or output. (TIM), and Section 14 ...
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... VOLTAGE IN/OUT LEVEL IN 4.0 to 5.5V OUT 0V V (3.3V) OUT REG V IN/OUT REG TST V IN REG V OUT REG IN 4.0 to 5.5V OUT 0V V (3.3V) OUT REGA0 V IN REGA0 V OUT REGA0 V OUT REGA0 V OUT REGA0 V OUT REGA0 V IN/OUT MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... PTE4 as D– of USB module. PTE4 as additional IRQ interrupt. Notes: 1. Pin available on 32-pin package only. 2. PTD[5:1] pins available on 28-pin package only. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Table 1-1. Summary of Pin Functions PIN DESCRIPTION General Description General Description VOLTAGE IN/OUT LEVEL ...
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... General Description Technical Data 40 General Description MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. In the memory map (Figure locations are shaded. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 41 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Input/Output (I/O) Section Figure 2-1, includes: ...
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... Break status and control register, BRKSCR • $FE0F; Reserved • $FFFF; COP control register, COPCTL Data registers are shown in locations. Technical Data 42 Figure 2-1 and in register figures in this document, Figure 2-2. Table 2-1 MC68HC908JB16 Memory Map is a list of vector Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor $0000 I/O Registers ↓ 128 Bytes $007F $0080 ↓ 384 Bytes $01FF $0200 Unimplemented ↓ 47,104 Bytes $B9FF $BA00 FLASH Memory ↓ 16,384 Bytes $F9FF $FA00 Monitor ROM 1 ↓ 1,024 Bytes $FDFF $FE00 SIM Break Status Register (SBSR) ...
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... DDRE4 Unimplemented Memory Map Bit 0 PTA3 PTA2 PTA1 PTA0 PTC1 PTC0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 DDRE3 DDRE2 DDRE1 DDRE0 Reserved MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... Register Low Write: (T1CH0L) Reset: Timer 1 Channel 1 Read: Status and Control Write: $0013 Register Reset: (T1SC1 Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 12) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit TOF TOIE TSTOP 0 TRST Bit15 Bit14 Bit13 ...
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... Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 TDX1FR TXD0FR RXD0FR RESUMFR TP2SIZ3 TP2SIZ2 TP2SIZ1 TP2SIZ0 PULLEN ENABLE2 ENABLE1 FUSBO FDP FDM PTE4IF PTE4IE IRQPD PTE3P PCP R PAP Reserved MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
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... USB Endpoint 0 Data $0026 Register 6 Write: UE0T67 (UE0D6) Reset: Read: UE0R77 USB Endpoint 0 Data $0027 Register 7 Write: UE0T77 (UE0D7) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 12) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit LVIDR LVI5OR3 URSTD LVID UE0R06 ...
Page 48
... UE1T31 UE1T30 UE1T43 UE1T42 UE1T41 UE1T40 UE1T53 UE1T52 UE1T51 UE1T50 UE1T63 UE1T62 UE1T61 UE1T60 UE1T73 UE1T72 UE1T71 UE1T70 UE2R03 UE2R02 UE2R01 UE2R00 UE2T03 UE2T02 UE2T01 UE2T00 UE2R13 UE2R12 UE2R11 UE2R10 UE2T13 UE2T12 UE2T11 UE2T10 R = Reserved MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 49
... Write: (UIR1) Reset: Read: USB Control Register 0 $003B Write: (UCR0) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 12) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit UE2R26 UE2R25 UE2R24 UE2T26 UE2T25 UE2T24 Unaffected by reset UE2R36 UE2R35 UE2R34 UE2T36 ...
Page 50
... Unimplemented Memory Map Bit 0 TP1SIZ2 TP1SIZ1 TP1SIZ0 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 RP2SIZ3 RP2SIZ2 RP2SIZ1 RP2SIZ0 PS2 PS1 PS0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Reserved MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 51
... Write: Reset: Read: $004E Reserved Write: Reset: Read: $004F Reserved Write: Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 12) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit CH0F CH0IE MS0B MS0A Bit15 Bit14 Bit13 Bit12 Indeterminate after reset Bit7 ...
Page 52
... Bit LOCK2 R R PLLON2 0 0 VCO_3 VCO_2 VCO_1 VCO_0 RDS1_9 RDS1_8 VDS1_3 VDS1_2 VDS1_1 VDS1_0 RDS1_3 RDS1_2 RDS1_1 RDS1_0 RDS2_9 RDS2_8 VDS2_3 VDS2_2 VDS2_1 VDS2_0 RDS2_3 RDS2_2 RDS2_1 RDS2_0 PHD_3 PHD_2 PHD_1 PHD_0 Reserved MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 53
... Reset: Read: $0061 Reserved Write: Reset: Read: $0062 Reserved Write: Reset: Read: $0063 Reserved Write: Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 12) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit LOOPS ENSCI TXINV SCTIE TCIE SCRIE DMARE DMATE U ...
Page 54
... Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 12) Technical Data 54 Bit POR PIN COP ILOP BCFE IF6 IF5 IF4 IF3 IF14 IF13 IF12 IF11 Unimplemented Memory Map Bit 0 SBSW Note 0 ILAD USB LVI IF2 IF1 IF10 IF9 IF8 IF7 Reserved MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 55
... Register (BRKL) Reset: Read: Break Status and Control $FE0E Register Write: (BRKSCR) Reset: Read: COP Control Register $FFFF Write: (COPCTL) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 12) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit BPR7 BPR6 BPR5 BPR4 ...
Page 56
... IF2 $FFF9 IRQ Vector (Low) $FFFA USB Vector (High) IF1 $FFFB USB Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) MC68HC908JB16 Memory Map Vector Rev. 1.1 — Freescale Semiconductor ...
Page 57
... RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Random-Access Memory (RAM) Technical Data 57 ...
Page 58
... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 58 Random-Access Memory (RAM) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 59
... This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Section 4. FLASH Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 62 FLASH Mass Erase Operation ...
Page 60
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 60 Bit BPR7 BPR6 BPR5 BPR4 Unimplemented FLASH Memory Bit 0 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 BPR0 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 61
... PGM bit should not be set the same time. PGM — Program Control Bit This read/write bit configures the memory for program operation. This bit and the ERASE bit should not be set the same time. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor $FE08 Bit ...
Page 62
... FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Technical Data 62 (5µs). nvs (10ms). Erase (5µs). nvh (1µs), the memory can be accessed in read mode rcv MC68HC908JB16 FLASH Memory Rev. 1.1 — Freescale Semiconductor ...
Page 63
... FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor register. $FFD0–$FFFF. (5µs). nvs (200ms). ...
Page 64
... FLASH memory. Technical Data 64 (5µs). nvs (10µs). pgs (30µs). Prog (5µs). nvh (1µs), the memory can be accessed in read mode rcv maximum. See 20.14 FLASH Memory Prog shows a flowchart representation for programming the FLASH Memory MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 65
... Prog This row program algorithm assumes the row programmed are initially erased. Figure 4-3. FLASH Programming Flowchart MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 1 Set PGM bit 2 Write any data to any FLASH address within the row address range desired 3 Wait for a time, t ...
Page 66
... Start address of FLASH block protect Technical Data 66 $FE09 Bit BPR7 BPR6 BPR5 BPR4 Figure 4-4. FLASH Block Protect Register (FLBPR) Figure 4-5. FLASH Block Protect Start Address FLASH Memory Bit 0 BPR3 BPR2 BPR1 BPR0 16-bit memory address BPR[7:1] MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 67
... ROM-resident routines can be called by a program running in user mode or in monitor mode (see programming, erasing, and verifying. The range of the FLASH memory must be unprotected (see erase or programming routine. Routine Name MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor BPR[7:0] $00 to $BA $BC (1011 1100) $BE (1011 1110) $C0 (1100 0000) $C2 (1100 0010) and so on... $FE ...
Page 68
... Data buffer for programming and verifying. Table 4-3. ERASE Routine ERASE $FC06 5 Bytes CPUSPD — CPU speed HX — Contains any address in the range to be erased CTRLBYT — Mass or block erase Mass erase if bit Block erase if bit FLASH Memory Description MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 69
... VERIFY Routine The VERIFY routine reads and verifies a range of FLASH memory. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Table 4-4. PROGRAM Routine Routine PROGRAM Calling Address $FC09 Stack Use 7 Bytes CPUSPD — ...
Page 70
... FLASH Memory Technical Data 70 MC68HC908JB16 FLASH Memory Rev. 1.1 — Freescale Semiconductor ...
Page 71
... MCU recommended that this register be written immediately after reset. The configuration register is located at $001F. The configuration register may be read at anytime. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Low voltage inhibit (LVI) module control and voltage trip point selection ...
Page 72
... REG (LVI).) disabled REG enabled REG . REGA Section 18. Low-Voltage Inhibit Section 11. Universal Serial Bus Module DD DD (LVI).) disabled DD enabled DD Configuration Register (CONFIG Bit 0 SSREC COPRS STOP COPD (See Section 18. Low- REG (LVI).) . (See Section 18. Low-Voltage MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 73
... COPD — COP Disable Bit COPD disables the COP module. (See Operating Properly MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 1 = Stop mode recovery after 2048 OSCDCLK cycles 0 = Stop mode recovery after 4096 OSCDCLK cycles 1 = COP timeout period COP timeout period STOP instruction enabled 0 = STOP instruction treated as illegal opcode (COP) ...
Page 74
... Configuration Register (CONFIG) Technical Data 74 Configuration Register (CONFIG) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 75
... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Stop Mode ...
Page 76
... Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64-Kbytes • Low-power stop and wait modes Technical Data 76 Central Processor Unit (CPU) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 77
... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor shows the five CPU registers. CPU registers are not part Figure 6-1. CPU Registers ...
Page 78
... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Read: Write: Reset: Technical Data 78 Bit Indeterminate Figure 6-3. Index Register (H:X) Bit Figure 6-4. Stack Pointer (SP) Central Processor Unit (CPU) Bit Bit MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 79
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Read: Write: Reset: MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit Loaded with Vector from $FFFE and $FFFF Figure 6-5 ...
Page 80
... The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor Carry between bits 3 and carry between bits 3 and 4 Technical Data 80 Bit Indeterminate Figure 6-6. Condition Code Register (CCR) Central Processor Unit (CPU Bit MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 81
... Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result 0 = Non-negative result 1 = Zero result 0 = Non-zero result ...
Page 82
... Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock. Technical Data 82 Central Processor Unit (CPU) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 83
... The opcode map is provided in MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock. ...
Page 84
... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 85
... Branch if Interrupt Mask Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? (N ⊕ ← (PC rel ? ( ⊕ ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← ...
Page 86
... DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 DIR INH 4F 1 INH 5F 1 INH 8C 1 IX1 SP1 9E6F ff 4 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 87
... Exclusive OR M with A EOR opr,X EOR ,X EOR opr,SP EOR opr,SP MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Description (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) (H:X) – ...
Page 88
... SP2 9ED6 IMM – DIR IMM DIR EXT IX2 – IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 44 1 INH 54 1 IX1 SP1 9E64 ff 5 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 89
... Rotate Right through Carry ROR opr,X ROR ,X ROR opr,SP RSP Reset Stack Pointer MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Description ← (M) (M) Destination Source H:X ← (H: (IX+D, DIX+) X:A ← (X) × (A) M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← ...
Page 90
... SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 SP2 9ED0 ee ff MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 91
... Indexed, 16-bit offset addressing mode M Memory location N Negative bit MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...
Page 92
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 ...
Page 93
... The 12MHz clock is required for various modules, such as the CGMs and USB. The clock doubler clock, OSCDCLK, is used as the base clock for the COP module. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Section 7. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .94 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Crystal Amplifier Input Pin (OSC1 Crystal Amplifier Output Pin (OSC1) ...
Page 94
... S 12 MHz C1 C2 higher frequency crystals. Refer to manufacturer’s data. Figure 7-1. Oscillator External Connections ) is included in the diagram to follow strict Pierce S Oscillator (OSC) 7-1. This figure shows only TO COP, SCI TO SIM OSCDCLK OSCOUT ÷ USB MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 95
... OSCDCLK is the clock doubler output signal. It runs at twice the speed of the crystal (f MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ) and comes directly from the crystal oscillator circuit. XCLK shows only the logical relation of OSCXCLK to OSC1 and ) and comes from the clock doubler circuit. ...
Page 96
... MCU. 7.5.2 Stop Mode The STOP instruction disables the OSCXCLK output. 7.6 Oscillator During Break Mode The oscillator continues to drive OSCXCLK when the chip enters the break state. Technical Data 96 MC68HC908JB16 Oscillator (OSC) ). This XCLK Rev. 1.1 — Freescale Semiconductor ...
Page 97
... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 100 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . 101 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 101 Reset and System Initialization 101 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Active Resets from Internal Sources ...
Page 98
... SIM Break Status Register (SBSR 118 SIM Reset Status Register (SRSR 119 SIM Break Flag Control Register (SBFCR 120 Figure shows the internal signal names used in this section. System Integration Module (SIM) 8-1. Figure 8 summary of MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 99
... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET ...
Page 100
... OSCDCLK FROM OSC OSCOUT Figure 8-3. SIM Clock Signals System Integration Module (SIM Bit 0 SBSW See note 0 ILAD USB LVI IF2 IF1 IF10 IF9 IF8 IF7 Figure 8-3. SIM COUNTER BUS CLOCK ÷ 2 GENERATORS SIM MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 101
... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Illegal opcode Illegal address Universal serial bus module (USB) Low-voltage inhibit module (LVI) System Integration Module (SIM) System Integration Module (SIM) 8 ...
Page 102
... Table 8-2. PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR/LVI All others PC Figure 8-4. External Reset Timing System Integration Module (SIM) 8.5 SIM Counter), but an 8.8 SIM Registers.) Table 8-2 for details. 4163 (4096 + ( VECT H VECT L MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 103
... The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Reset.) 8-5. IRST RST PULLED LOW BY MCU RST 32 CYCLES IAB Figure 8-5 ...
Page 104
... The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. OSC1 PORRST OSCDCLK OSCOUT RST IAB Technical Data 104 4096 32 32 CYCLES CYCLES CYCLES Figure 8-7. POR Recovery System Integration Module (SIM) $FFFE $FFFF MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 105
... MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 12 4 – 2 OSCDCLK cycles, drives the COP counter. The COP System Integration Module (SIM) ...
Page 106
... Some registers are reset by POR or LVI reset only. registers or register bits which are unaffected by normal resets. Technical Data 106 or V voltage falls to the LVI reset voltage, V REG (CONFIG).) System Integration Module (SIM) . The LVI bit TRIP Section 5. Configuration Table 8-3 shows the MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 107
... The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Table 8-3. Registers not Affected by Normal Reset Bits Registers CONFIG URSTD, LVID ...
Page 108
... Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. system interrupts. Technical Data 108 Figure 8-8 System Integration Module (SIM) 8.7.2 Stop Mode for counter control and flow charts the handling of MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 109
... YES (As many interrupts as exist on chip) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES USB INTERRUPT? NO YES IRQ INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. YES SWI INSTRUCTION? NO YES RTI INSTRUCTION? NO Figure 8-8. Interrupt Processing ...
Page 110
... SP – – – – CCR . Figure 8-9 Interrupt Entry SP – – – – 1[15:8] PC – 1 [7:0] OPCODE Figure 8-10. Interrupt Recovery System Integration Module (SIM) Figure VECT H VECT L START ADDR V DATA H V DATA L OPCODE OPERAND MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 111
... If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor CLI LDA #$FF INT1 PSHH PULH ...
Page 112
... Bit 1 and Bit 0 — Always read 0 Technical Data 112 Table 8-4 summarizes the interrupt sources and the interrupt $FE04 Bit IF6 IF5 IF4 IF3 Reserved Figure 8-12. Interrupt Status Register 1 (INT1) Table 8-4. System Integration Module (SIM Bit 0 IF2 IF1 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 113
... SCI transmission complete Keyboard interrupt Notes: 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction. 2. Highest priority = 0. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Table 8-4. Interrupt Sources INT Register (1) Flags Mask None None ...
Page 114
... Technical Data 114 $FE05 Bit IF14 IF13 IF12 IF11 Reserved Figure 8-13. Interrupt Status Register 2 (INT2) Table 8-4. (BRK).) The SIM puts the CPU into the System Integration Module (SIM Bit 0 IF10 IF9 IF8 IF7 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 115
... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Figure 8-14 shows the timing for wait mode entry. System Integration Module (SIM) System Integration Module (SIM) Technical Data ...
Page 116
... Figure 8-15. Wait Recovery from Interrupt or Break 32 CYCLES CYCLES $6E0B $A6 $A6 $A6 Figure 8-16. Wait Recovery from Internal Reset System Integration Module (SIM) SAME SAME SAME SAME $00FE $00FD $00FC $6E 32 RST VCT H RST VCT L MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 117
... CPUSTOP OSCDCLK INT/BREAK IAB Figure 8-18. Stop Mode Recovery from Interrupt or Break MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Figure 8-17 shows stop mode entry timing. IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction Figure 8-17 ...
Page 118
... The following code is an example of this. Writing 0 to the SBSW bit clears it. Technical Data 118 $FE00 Bit Figure 8-19. SIM Break Status Register (SBSR) System Integration Module (SIM Bit 0 SBSW Note Reserved MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 119
... PIN bit in the SRSR may be set in addition to whatever other bits are set. Address: Read: Write: POR: POR — Power-On Reset Bit MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ...
Page 120
... The SIM break flag control register contains a bit that enables software to clear status bits while the MCU break state. Address: Read: Write: Reset: Figure 8-21. SIM Break Flag Control Register (SBFCR) Technical Data 120 $FE03 Bit BCFE Reserved System Integration Module (SIM Bit MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 121
... MCU break state. To clear status bits during the break state, the BCFE bit must be set. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 1 = Status bits clearable during break 0 = Status bits not clearable during break System Integration Module (SIM) System Integration Module (SIM) ...
Page 122
... System Integration Module (SIM) Technical Data 122 System Integration Module (SIM) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 123
... Monitor mode entry can be achieved without use of the higher voltage, V TST reducing the hardware requirements for in-circuit programming. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Section 9. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Break Signal ...
Page 124
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 124 1 Figure 9-1 shows a example circuit used to enter monitor Monitor ROM (MON reset vector is TST , is applied to TST MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 125
... SW2: Position D — Low-voltage entry to monitor mode (with blank reset vector). See Section 20. for IRQ voltage level requirements. 3. SW3: Position E — OSC1 directly driven by external oscillator. SW3: Position F — OSC1 driven by crystal oscillator circuit. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor V V TST DD 10k Ω 10k Ω C (SEE NOTE 2) D 4.7 µ ...
Page 126
... High-voltage entry to monitor mode. ÷ 2) 19200 baud communication on PTA0. COP disabled. Low-voltage entry to monitor mode. ÷ 2) 19200 baud communication on PTA0. COP disabled. Enters user mode. If $FFFE and $FFFF is ÷ 2) blank, MCU will encounter an illegal address reset. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 127
... Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the state of IRQ or the RST. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor is applied to IRQ and PTA3 is low upon monitor mode entry TST condition set 1), the bus frequency is a equal to the external . If PTA3 is high with V ...
Page 128
... IRQ pin or the RST pin, the SIM asserts its TST Monitor ROM (MON external clock of 12MHz is Figure 9-1 by Break Break SWI SWI Vector Vector Vector Vector High Low High Low $FFFC $FFFD $FFFC $FFFD $FEFC $FEFD $FEFC $FEFD MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 129
... The communication baud rate is dependant on oscillator frequency, f XCLK is by IRQ = V PTA3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 312. Blank reset vector, MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor START BIT 0 BIT 1 BIT 2 BIT 3 BIT Figure 9-3. Monitor Data Format MISSING STOP BIT 0 ...
Page 130
... Data return delay, 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Technical Data 130 ADDRESS ADDRESS ADDRESS READ HIGH HIGH LOW Figure 9-5. Read Transaction Monitor ROM (MON) ADDRESS DATA LOW RETURN MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 131
... ECHO Notes: A brief description of each monitor mode command is given in Table 9-4 Description Operand Returned MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor FROM HOST ADDRESS ADDRESS WRITE WRITE HIGH HIGH Echo delay, 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte. ...
Page 132
... Read next 2 bytes in memory from last address accessed Specifies 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence SENT TO MONITOR IREAD IREAD ECHO Monitor ROM (MON) DATA DATA LOW DATA DATA RETURN MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 133
... A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64k-byte memory map. Description Operand Returned MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Table 9-7. IWRITE (Indexed Write) Command Write to last address accessed + 1 Specifies single data byte Data None Opcode $19 ...
Page 134
... SENT TO MONITOR RUN RUN ECHO HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER Figure 9-7. Stack Pointer at Monitor Mode Entry Monitor ROM (MON MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 135
... PTA0 NOTES Echo delay, 2 bit times Data return delay, 2 bit times Wait 1 bit time before sending next byte. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Figure 9-8.) 4096 + 32 OSCDCLK CYCLES 256 BUS CYCLES (MINIMUM) FROM HOST 1 FROM MCU Figure 9-8. Monitor Mode Entry Timing ...
Page 136
... Read/write of RAM and FLASH. Read/write of RAM. FAILED Read of FLASH disabled. FLASH can only be mass erased. BYPASSED Read/write of RAM and FLASH disabled. Read/write of RAM. FAILED Read of FLASH disabled. FLASH can only be mass erased. Monitor ROM (MON) Monitor Functions Available MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 137
... TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 155 10.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 156 10.10.5 TIM Channel Registers 159 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Section 10. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 TIM Counter Prescaler ...
Page 138
... External TIM clock input (bus frequency ÷2 maximum) • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits Technical Data 138 Timer Interface Module (TIM) Figure 10 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 139
... Output compare functions should only be enabled for one channel to avoid I/O contention. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Table 10-1. The generic pin names appear in the Table 10-1. Pin Name Conventions TIM Generic Pin Names: TIM1 ...
Page 140
... ELS0A CH1MAX CH1F CH01IE MS0A Figure 10-1. TIM Block Diagram summarizes the timer registers. Timer Interface Module (TIM) TOF INTERRUPT LOGIC TOIE TOV0 PORT LOGIC INTERRUPT T[1,2]CH01 LOGIC CH0IE TOV1 PORT LOGIC INTERRUPT LOGIC CH1IE MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 141
... Reset: Read: Timer 1 Channel 0 $0012 Register Low Write: (T1CH0L) Reset: Read: Timer 1 Channel 1 Status $0013 and Control Register Write: (T1SC1) Reset: Figure 10-2. TIM I/O Register Summary (Sheet MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit TOF 0 TOIE TSTOP 0 TRST Bit ...
Page 142
... TSTOP 0 TRST Bit Bit Bit Bit CH0F CH0IE MS0B MS0A Bit Indeterminate after reset = Unimplemented Timer Interface Module (TIM Bit Bit Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit 8 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 143
... When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit Bit ...
Page 144
... Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. Technical Data 144 10.5.3 Output Compare. The pulses are Timer Interface Module (TIM) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 145
... TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Figure 10-3 shows, the output compare value in the TIM channel Timer Interface Module (TIM) Timer Interface Module (TIM) Technical Data ...
Page 146
... TIM Status and Control OVERFLOW PERIOD PULSE WIDTH OUTPUT COMPARE Figure 10-3. PWM Period and Pulse Width 10.5.4 Pulse Width Modulation Timer Interface Module (TIM) Register. OVERFLOW OUTPUT OUTPUT COMPARE COMPARE (PWM). The pulses are MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 147
... I/O pin. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value ...
Page 148
... Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Timer Interface Module (TIM) Table 10-3.) Table 10-3.) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 149
... The WAIT and STOP instructions put the MCU in low power- consumption standby modes. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Registers.) TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests ...
Page 150
... BCFE is at logic 0. After the break, doing the second step clears the status bit. Technical Data 150 8.8.3 SIM Break Flag Control (SBFCR).) Timer Interface Module (TIM) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 151
... TIM Channel I/O Pins (PTE1/T1CH01:PTE2/T2CH01) Each TIM I/O pin is programmable independently as an input capture pin or an output compare pin, or configured as buffered output compare or buffered PWM pins. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 10.10.1 TIM Status and Control or TCLK LMIN HMIN 1 ------------------------------------ - bus frequency bus frequency ÷ ...
Page 152
... Address: T1SC, $000A and T2SC, $0040 Read: Write: Reset: Technical Data 152 Bit TOF 0 TOIE TSTOP 0 TRST Unimplemented Figure 10-4. TIM Status and Control Register (TSC) Timer Interface Module (TIM Bit 0 0 PS2 PS1 PS0 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 153
... Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled ...
Page 154
... Reset clears the TIM Clock Source Internal bus clock ÷ 1 Internal bus clock ÷ 2 Internal bus clock ÷ 4 Internal bus clock ÷ 8 Internal bus clock ÷ 16 Internal bus clock ÷ 32 Internal bus clock ÷ 64 TCLK Bit Bit MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 155
... Read: Write: Reset: Address: T1MODL, $000F and T2MODL, $0045 Read: Write: Reset: NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit Bit Unimplemented Figure 10-6. TIM Counter Registers Low (TCNTL) Bit 7 ...
Page 156
... TIM channel x registers. Technical Data 156 Bit CH0F CH0IE MS0B MS0A Bit CH1F CH1IE CH01IE MS1A Timer Interface Module (TIM Bit 0 ELS0B ELS0A TOV0 CH0MAX Bit 0 ELS1B ELS1A TOV1 CH1MAX MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 157
... See MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 1 = Input capture or output compare on channel input capture or output compare on channel Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled 1 = CPU interrupt requests when CH0F and CH1F are set ...
Page 158
... Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 159
... The state of the TIM channel registers after reset is unknown. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 1 = Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow shows, the CHxMAX bit takes effect in the cycle after it OVERFLOW ...
Page 160
... Indeterminate after reset Figure 10-14. TIM Channel 1 Register High (TCH1H) Bit Bit Indeterminate after reset Figure 10-15. TIM Channel 1 Register Low (TCH1L) Timer Interface Module (TIM Bit Bit Bit Bit Bit Bit Bit Bit 0 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 161
... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Address Field (ADDR 172 Endpoint Field (ENDP 172 Cyclic Redundancy Check (CRC) ...
Page 162
... USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . . 201 Receive Control Endpoint 202 Transmit Control Endpoint 204 Transmit Endpoint 205 Transmit Endpoint 206 Receive Endpoint 206 Resume Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Universal Serial Bus Module (USB) 2.0. Control and interrupt data MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 163
... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Universal Serial Bus Specification 2.0 low-speed functions 1.5 Mbps data rate On-chip 3.3V regulator Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer Endpoint 1 with 8-byte transmit buffer Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer USB data control logic: – ...
Page 164
... PTE4/D– Bit TXD1FR TXD0FR RXD0FR RESUMFR TP2SIZ3 TP2SIZ2 TP2SIZ1 TP2SIZ0 PULLEN ENABLE2 ENABLE1 FUSBO FDP FDM UE0R03 UE0R02 UE0R01 UE0R00 UE0T03 UE0T02 UE0T01 UE0T00 UE0R13 UE0R12 UE0R11 UE0R10 UE0T13 UE0T12 UE0T11 UE0T10 U = Unaffected by reset MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 165
... Register 2 Write: UE1T27 (UE1D2) Reset: Read: USB Endpoint 1 Data $002B Register 3 Write: UE1T37 (UE1D3) Reset: Figure 11-1. USB I/O Register Summary (Sheet MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit UE0R26 UE0R25 UE0R24 UE0T26 UE0T25 UE0T24 Unaffected by reset UE0R36 UE0R35 UE0R34 UE0T36 ...
Page 166
... UE2T10 UE2R23 UE2R22 UE2R21 UE2R20 UE2T23 UE2T22 UE2T21 UE2T20 UE2R33 UE2R32 UE2R31 UE2R30 UE2T33 UE2T32 UE2T31 UE2T30 UE2R43 UE2R42 UE2R41 UE2R40 UE2T43 UE2T42 UE2T41 UE2T40 UE2R53 UE2R52 UE2R51 UE2R50 UE2T53 UE2T52 UE2T51 UE2T50 U = Unaffected by reset MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 167
... USB Status Register 0 $003D Write: (USR0) Reset: Read: R2SEQ USB Status Register 1 $003E Write: (USR1) Reset: Figure 11-1. USB I/O Register Summary (Sheet MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Bit UE2R66 UE2R65 UE2R64 UE2T66 UE2T65 UE2T64 Unaffected by reset UE2R76 UE2R75 UE2R74 UE2T76 ...
Page 168
... USB module. The USB Description). RCV VPIN USB VMIN CONTROL LOGIC VPOUT VMOUT FROM OSC USB REGISTERS Figure 11-2. USB Block Diagram Universal Serial Bus Module (USB USB UPSTREAM PORT D – 6MHZ MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 169
... SETUP DATA0 ENDPOINTS 1 & 2 TRANSACTIONS: Interrupt IN DATA0/1 Bulk Transmit IN DATA0/1 Figure 11-3. Supported Transaction Types Per Endpoint MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor shows the various transaction types supported by the USB ACK OUT DATA0 ACK ACK IN DATA0 ACK ACK IN ACK ACK ...
Page 170
... Figure 11-4. Supported USB Packet Types Figure 11-5 SYNC PATTERN Idle Figure 11-5. Sync Pattern Universal Serial Bus Module (USB) Figure 11-4. Token packets ADDR ENDP CRC5 EOP DATA CRC16 EOP 0 – 8 Bytes EOP is used as a synchronization PID0 PID1 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 171
... The packet identifier field is an 8-bit number comprised of the 4-bit packet identification and its complement. The field follows the sync pattern and determines the direction and type of transaction on the bus. Table 11-2 types. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor (min.) (max) (min.) (min FIRST BIT OF PACKET ...
Page 172
... D+ and D– output drivers are placed in their high- impedance state. The bus termination resistors hold the bus in the idle state. Figure 11-7 end-of-packet transaction. Technical Data 172 shows the data signaling and voltage levels for an Universal Serial Bus Module (USB) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 173
... USB bus. The USB bit in the reset status register (SRSR) will be set after the internal reset is removed. Refer to Status Register (SRSR) sequence is detailed in MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor (min.) (max) (min.) (min Figure 11-7. EOP Transaction Voltage Levels ...
Page 174
... USB module has been placed in the suspend state. Technical Data 174 for more detail. (CONFIG)). When a USB reset is detected, the supply when in the suspend state. DD Universal Serial Bus Module (USB) 11.8.3 USB Interrupt Section 5. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 175
... Refer to register definitions (see more information about how the force resume (FRESUM) bit can be used to initiate the remote wakeup feature. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 11.8.6 USB Control Register Universal Serial Bus Module (USB) Universal Serial Bus Module (USB) 1) for Technical Data ...
Page 176
... The jitter in the low-speed data rate must be less than 10ns. Technical Data 176 Figure 11-9 with the pull-up on the D– line. V (3.3V) REG 1.5 kΩ MCU D+ D– ± 1.5% (15,000 ppm). This tolerance Universal Serial Bus Module (USB) USB LOW-SPEED CABLE MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 177
... USB Transceiver The USB transceiver provides the physical interface to the USB D+ and D– data lines. The transceiver is composed of two parts: an output drive circuit and a receiver. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 4.0V TO 5.5V 3.3V USB DATA LINES REGULATOR R1 D+ LOW-SPEED TRANSCEIVER D– ...
Page 178
... The OH ONE BIT TIME (1.5 Mb/s) REFLECTIONS AND RINGING Figure 11-11. Receiver Characteristics Universal Serial Bus Module (USB) ± 20% to minimize SIGNAL PINS PASS OUTPUT SPEC LEVELS WITH MINIMAL MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 179
... The data jitter is measured with the same capacitive load used for maximum rise and fall times and is measured at the crossover points of the data lines as shown in MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor Figure Differential Input voltage Range Differential Output 0.0 0.2 0.4 ...
Page 180
... DATA LINES 10 LOW SPEED: 75ns at C Figure 11-14. Data Signal Rise and Fall Time Universal Serial Bus Module (USB) CROSSOVER POINTS ± ± 25ns and within 10ns for ) of 200pF L FALL TIME 90% 90% 10 200pF, 300ns 600 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 181
... MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor USB address register (UADDR) USB control registers 0–4 (UCR0–UCR4) USB status registers 0–1 (USR0–USR1) USB interrupt registers 0–2 (UIR0–UIR2) USB endpoint 0 data registers 0–7 (UE0D0–UE0D7) USB endpoint 1 data registers 0–7 (UE1D0–UE1D7) USB endpoint 2 data registers 0– ...
Page 182
... These bits specify the USB address of the device. Reset clears these bits. Technical Data 182 $0038 Bit USBEN UADD6 UADD5 UADD4 Figure 11-15. USB Address Register (UADDR) interrupt Universal Serial Bus Module (USB Bit 0 UADD3 UADD2 UADD1 UADD0 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 183
... TXD2IE — Endpoint 2 Transmit Interrupt Enable This read/write bit enables the transmit endpoint 2 to generate CPU interrupt requests when the TXD2F bit becomes set. Reset clears the TXD2IE bit. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor $0039 Bit EOPIE SUSPND TXD2IE ...
Page 184
... RXD0F bit becomes set. Reset clears the RXD0IE bit Receive endpoint 0 can generate a CPU interrupt request 0 = Receive endpoint 0 cannot generate a CPU interrupt request Technical Data 184 Universal Serial Bus Module (USB) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 185
... ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD2FR bit. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor $003A Bit EOPF ...
Page 186
... SUSPND bit is set. Software must clear this flag by writing a logic 1 to the RESUMFR bit. Reset clears this bit. Writing a logic 0 to RESUMF has no effect USB bus activity has been detected USB bus activity has been detected Technical Data 186 Universal Serial Bus Module (USB) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 187
... OUT tokens; but does not respond to a SETUP token. Reset clears this bit. Writing to RXD0F has no effect. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 1 = Transmit on endpoint 0 has occurred 0 = Transmit on endpoint 0 has not occurred 1 = Receive on endpoint 0 has occurred 0 = Receive on endpoint 0 has not occurred ...
Page 188
... Writing a logic 0 to RXD0FR has no effect. Reset clears this bit. Technical Data 188 $0018 Bit EOPFR RSTFR TXD2FR RXD2FR Figure 11-18. USB Interrupt Register 2 (UIR2) Universal Serial Bus Module (USB Bit TXD1FR TXD0FR RXD0FR RESUMFR MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 189
... If this bit the RXD0F is set, the USB will respond with a NAK handshake to any endpoint 0 OUT tokens; but does not respond to a SETUP token. Reset clears this bit. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor $003B Bit T0SEQ TX0E ...
Page 190
... It must be cleared by software when no more data needs to be transmitted. Technical Data 190 $003C Bit T1SEQ STALL1 TX1E FRESUM TP1SIZ3 Figure 11-20. USB Control Register 1 (UCR1) Universal Serial Bus Module (USB Bit 0 TP1SIZ2 TP1SIZ1 TP1SIZ0 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 191
... DATA1) will be sent during the next IN transaction directed to endpoint 2. Toggling of this bit must be controlled by software. Reset clears this bit. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor 1 = Data is ready to be sent 0 = Data is not ready. Respond with NAK 1 = Force data lines to K state 0 = Default $0019 ...
Page 192
... TP2SIZ3–TP2SIZ0 — Endpoint 2 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for endpoint 2. These bits are cleared by reset. Technical Data 192 Universal Serial Bus Module (USB) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 193
... This read/write bit causes endpoint 0 to return a STALL handshake when polled by an OUT token by the USB host controller. The USB hardware clears this bit when a SETUP token is received. Reset clears this bit. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor $001A Bit TX1ST 0 ...
Page 194
... This read/write bit enables endpoint 1 and allows the USB to respond to IN packets addressed to endpoint 1. Reset clears this bit Endpoint 1 is enabled and can respond token 0 = Endpoint 1 is disabled Technical Data 194 Universal Serial Bus Module (USB) MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 195
... FUSBO and the USBEN bits are set, the USB module is in output mode and it will not recognize any USB signals including the USB reset signal. The UCR4 register is used for some special applications. Customers are not normally expected to use this register. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor $001B Bit ...
Page 196
... These read-only bits store the number of data bytes received for the last OUT or SETUP transaction for endpoint 0. Technical Data 196 $003D Bit R0SEQ SETUP 0 0 Unaffected by reset = Unimplemented Figure 11-24. USB Status Register 0 (USR0) Universal Serial Bus Module (USB Bit 0 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 197
... This bit is updated at the end of the data transmission. RP2SIZ3–RP2SIZ0 — Endpoint 2 Receive Data Packet Size These read-only bits store the number of data bytes received for the last OUT transaction for endpoint 2. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor $003E Bit R2SEQ TXACK ...
Page 198
... Unaffected by reset ↓ $0027 UE0D7 UE0R76 UE0R75 UE0R74 UE0T76 UE0T75 UE0T74 Unaffected by reset Universal Serial Bus Module (USB Bit 0 UE0R03 UE0R02 UE0R01 UE0R00 UE0T03 UE0T02 UE0T01 UE0T00 ↓ UE0R73 UE0R72 UE0R71 UE0R70 UE0T73 UE0T72 UE0T71 UE0T70 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...
Page 199
... Figure 11-27. USB Endpoint 1 Data Registers (UE1D0–UE1D7) UE1Tx7–UE1Tx0 — Endpoint 1 Transmit or Receive Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at endpoint 1. MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor $0028 UE1D0 Bit ...
Page 200
... Unaffected by reset ↓ $0037 UE2D7 UE2R76 UE2R75 UE2R74 UE2T76 UE2T75 UE2T74 Unaffected by reset Universal Serial Bus Module (USB Bit 0 UE2R03 UE2R02 UE2R01 UE2R00 UE2T03 UE2T02 UE2T01 UE2T00 ↓ UE2R73 UE2R72 UE2R71 UE2R70 UE2T73 UE2T72 UE2T71 UE2T70 MC68HC908JB16 Rev. 1.1 — Freescale Semiconductor ...