MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 1124

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Internal Memory Map
B-14
1
2
3
4
5
0x30 45E0 –
0x30 45EF
0x30 45F0 –
0x30 45FF
0x30 4800
0x30 4802
0x30 4804
0x30 4806
0x30 4808
0x30 480A
0x30 480C
0x30 480E
0x30 4810
Bit 10 (TPU3) and bit 11 (T2CSL) are write-once. Bits 1:2 (TCR1P) and bits 3:4 (TCR2P) are write-once if PWOD is
not set in the TPUMCR3 register. This register cannot be accessed with a 32-bit read. It can only be accessed with an
8- or 16-bit read.
Some TPU registers can only be read or written with 16- or 32-bit accesses. 8-bit accesses are not allowed.
S/U = Supervisor accessible only if SUPV = 1 or unrestricted if SUPV = 0. Unrestricted registers allow both user and
supervisor access. The SUPV bit is in the TPUMCR register.
TPU code development (Debug) register
Bits 9:10 (ETBANK), 14 (T2CF), and 15 (DTPU) are write-once.
Address
Address
Access
Table B-9. Time Processor Unit 3 A and B (TPU3 A and B) (continued)
Table B-10. QADC64E A and B (Queued Analog-to-Digital Converter)
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S
S
S
3
3
1
1
QADC64MCR_A QADC64 Module Configuration Register.
QADC64INT_A
QADC64TST
PORTQA_A/
Symbol
PORTQB_A
DDRQA_A/
DDRQB_A
QACR0_A
QACR1_A
QACR2_A
QASR0_A
(Note: Bit descriptions apply to QADC_B as well)
Symbol
MPC561/MPC563 Reference Manual, Rev. 1.2
—
—
TPU3_B Channel 14 Parameter Registers
TPU3_B Channel 15 Parameter Registers
See
descriptions.
QADC64 Test Register.
Interrupt Register.
See
descriptions.
Port A and Port B Data.
See
descriptions.
Port A Data and Port B Direction Register.
See
more information.
QADC64 Control Register 0.
See
descriptions.
QADC64 Control Register 1.
See
descriptions.
QADC64 Control Register 2.
See
descriptions.
QADC64 Status Register 0.
See
descriptions.
Table 13-5
Section 13.2.2
Section 13.3.4
Table 13-9
Table 13-10
Table 13-12
Table 13-14
QADC_A
Table 1-9
and
and
and
and
and
and
Register
Register
Table 14-8
and
and
Table 14-5
Table 14-9
Table 14-11
Table 14-13
Table 14-15
Section 14.3.2
Section 14.3.4
for bit
for bit
for bit
for bit
for bit
for bit
for bit
for
Freescale Semiconductor
16, 32
Size
Size
16
16
16
16
16
16
16
16
16
16
2
2
Reset
Reset
S
S
S
U
S
S
S
S
S
—
—