MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 12

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
9.5.2.1
9.5.2.2
9.5.2.3
9.5.3
9.5.3.1
9.5.3.2
9.5.4
9.5.5
9.5.6
9.5.7
9.5.7.1
9.5.7.2
9.5.7.3
9.5.7.4
9.5.8
9.5.8.1
9.5.8.2
9.5.8.3
9.5.8.4
9.5.8.5
9.5.8.6
9.5.8.7
9.5.9
9.5.9.1
9.5.9.2
9.5.9.3
9.5.9.4
9.5.10
9.5.11
9.5.11.1
9.5.11.2
Freescale Semiconductor
Paragraph
Number
Features ........................................................................................................................... 9-1
Bus Transfer Signals ....................................................................................................... 9-1
Bus Control Signals ........................................................................................................ 9-2
Bus Interface Signal Descriptions ................................................................................... 9-3
Bus Operations ................................................................................................................ 9-8
Basic Transfer Protocol .............................................................................................. 9-8
Single Beat Transfer ................................................................................................... 9-9
Data Bus Pre-Discharge Mode ................................................................................. 9-15
Burst Transfer ........................................................................................................... 9-17
Burst Mechanism ...................................................................................................... 9-18
Alignment and Packaging of Transfers .................................................................... 9-29
Arbitration Phase ...................................................................................................... 9-32
Address Transfer Phase Signals ................................................................................ 9-37
Termination Signals .................................................................................................. 9-40
Storage Reservation .................................................................................................. 9-42
Bus Exception Control Cycles .................................................................................. 9-45
Single Beat Read Flow ........................................................................................... 9-9
Single Beat Write Flow ........................................................................................ 9-11
Single Beat Flow with Small Port Size ................................................................. 9-14
Operating Conditions ............................................................................................ 9-16
Initialization Sequence .......................................................................................... 9-16
Bus Request .......................................................................................................... 9-33
Bus Grant .............................................................................................................. 9-33
Bus Busy ............................................................................................................... 9-34
Internal Bus Arbiter .............................................................................................. 9-35
Transfer Start ........................................................................................................ 9-37
Address Bus .......................................................................................................... 9-37
Read/Write ............................................................................................................ 9-37
Burst Indicator ...................................................................................................... 9-37
Transfer Size ......................................................................................................... 9-38
Address Types ...................................................................................................... 9-38
Burst Data in Progress .......................................................................................... 9-40
Transfer Acknowledge .......................................................................................... 9-40
Burst Inhibit .......................................................................................................... 9-40
Transfer Error Acknowledge ................................................................................ 9-40
Termination Signals Protocol ............................................................................... 9-40
Retrying a Bus Cycle ............................................................................................ 9-45
Termination Signals Protocol Summary ............................................................... 9-49
MPC561/MPC563 Reference Manual, Rev. 1.2
External Bus Interface
Contents
Chapter 9
Title
Number
Page
xii