MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 121
MPC564MZP66
Manufacturer Part Number
MPC564MZP66
Description
IC MCU 512K FLASH 66MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP66
Core Processor
PowerPC
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Price
Company:
Part Number:
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Manufacturer:
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Quantity:
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2.4
The PDMCR2 controls alternate functionality of signals shared between different modules, as well as the
pre-discharge circuitry to allow 5V friendliness on the data bus.
Freescale Semiconductor
1
15-31
HRESET
HRESET
9:14
Bits
This bit was RESERVED on the K27S mask set of MPC561.
6
7
8
Field PREDIS_ EN
Addr
Field
Pad Module Configuration Register (PDMCR2)
T2CLK_PU Controls the pull-up on the TPU T2CLK signals.
PULL_DIS
SPRDS
PRDS
Name
—
PPMV
MSB
16
0
Disables weak pull-up/pull down devices enabled at the assertion of PORESET/TRST or
HRESET.
Signals affected by the PRDS bit include the following:
0 Enable weak pull-up/pull down devices on pads controlled by this signal.
1 Disable weak pull-up/pull down devices on pads controlled by this signal.
Refer to
Disables weak pull-up/pull down devices enabled at the assertion of PORESET/TRST or
HRESET.
Signals affected by the SPRDS bit include the following: BDIP, TA, TS, TEA, RD/WR, BR, BG, BB,
TSIZ, BI/STS, BURST, TDI, TMS, JCOMP, TCK.
0 Enable weak pull-up/pull down devices on pads controlled by this signal.
1 Disable weak pull-up/pull down devices on pads controlled by this signal.
Refer to
0 Pull-ups are enabled if the T2CLK signals are defined as inputs
1 Pull-ups are disabled on the T2CLK signals
Disables weak pull up-or-down devices enabled at the assertion of PORESET/TRST or HRESET.
Signals affected by these bits include the following:
0 Enable weak pull-up/pull-down devices on pads controlled by this signal.
1 Disable weak pull-up/pull-down devices on pads controlled by this signal.
Reserved
• all SGPIO signals
• all TPU3 signals
• PULL_DIS0 (bit 9): all MIOS14 input signals
• PULL_DIS1 (bit 10): all QSMCM input signals
• PULL_DIS2 (bit 11): all QADC64E input signals, except ETRIG1 and ETRIG2
• PULL_DIS3 (bit 12): all TouCAN input signals
• PULL_DIS4 (bit 13): Reserved
• PULL_DIS5 (bit 14): ETRIG1 and ETRIG2
Figure 2-3. Pads Module Configuration Register 2 (PDMCR2)
17
1
Table 2-5. PDMCR Field Descriptions (continued)
Table 2-14
Table 2-14
—
—
18
2
MPC561/MPC563 Reference Manual, Rev. 1.2
19
3
MDO6 MPI6
for more information on PRDS.
for more information on SPRDS.
20
4
TCNC
21
5
0000_0000_0000_0000
0000_0000_0000_0000
MPI7 MPI8 MPI9
22
6
0x2F C038
Description
—
23
7
1
24
8
PC
SV
25
9
—
PCS
4EN
10
26
PCS
5EN
11
27
PPMPAD
PCS
6EN
12
28
PCS
7EN
13
29
Signal Descriptions
14
30
—
—
LSB
15
31
2-23
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