MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 135

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Freescale Semiconductor
SGPIOC6
Signal List
SGPIOC7
VFLS[0:1]
IWP[0:1]
IRQOUT /
BB
LWP1
DSCK /
IWP2
IWP3
DSDI /
VF0
VF1
VF2
LWP0
TMS /
FRZ /
BG
TCK /
MCKI
BR
MDI0
EVTI
TDI /
PTR
7, 12
7
7
7
7
7
/
/
/
/
7
/
7
7
/
7
3
3
/
7
1
/
/
Voltage
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
5 V
5 V
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Controlled
Slew Rate
Option?
Yes
Yes
MPC561/MPC563 Reference Manual, Rev. 1.2
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
50 ; 50
50 ; 50
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
Drive
Load
(pF)
NA
NA
NA
NA
NA
NA
NA
NA
JTAG/BDM/READI
2
5
5
PD until PRDS
is set
PD until reset
negates
PD until reset
negates
PD until PRDS
is set
PD until reset
negates
PD until reset
negates
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 until reset
negates
PU2.6 if in JTAG
mode, otherwise
PD until SPRDS
is set
PU2.6 if in JTAG
mode, otherwise
PD until SPRDS
is set
PD until reset
negates
Reset State
14
6
6
6
6
Hysteresi
Enabled?
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
s
PTR
LWP0
Controlled by DBGC in reset
config word. See
Controlled by DBGC in reset
config word. See
Controlled by DBGC in reset
config word. See
Controlled by DBGC in the
reset config word. See
Table
TMS unless the Nexus
(READI) port is enabled, then
EVTI. See
DSDI unless the Nexus
(READI) port (MDI0) or JTAG
mode (TDI) is enabled. See
Section
DSCK unless the Nexus
(READI) port (MCKI) or JTAG
mode (TCK) is enabled. See
Section
Function After HRESET,
6-8.
PORESET/TRST
2.5.
2.5.
Section
Signal Descriptions
Table
Table
Table
2.5.
6-8.
6-8.
6-8.
2-37