MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 200

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Central Processing Unit
When a floating-point exception is taken, instruction execution resumes at offset 0x0E00 from the base
address indicated by MSR[IP].
3.15.4.13 Implementation-Dependent Software Emulation Exception (0x1000)
An implementation-dependent software emulation exception occurs in the following instances:
Table 3-34
3-56
1
•
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Machine State Register (MSR)
When executing any non-implemented instruction. This includes all illegal and unimplemented
optional instructions and all floating-point instructions.
When executing a mtspr or mfspr instruction that specifies an un-implemented
internal-to-the-processor SPR, regardless of the value of bit 0 of the SPR.
When executing a mtspr or mfspr that specifies an un-implemented external-to-the-processor
register and SPR0 = 0 or MSR[PR] = 0 (no program interrupt condition).
shows the register settings set when a software emulation exception occurs.
Register Name
Register Name
Table 3-33. Register Settings following Floating-Point Assist Exceptions
Table 3-34. Register Settings following a Software Emulation Exception
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
10:15
Other
Other
10:15
Other
Bits
Bits
ME
1:4
1:4
LE
All
IP
Cleared to 0
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Set to the effective address of the instruction that caused the
interrupt
Cleared to 0
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
No change
Cleared to 0
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
Description
Description
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