MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 317

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MPC564MZP66

Manufacturer Part Number
MPC564MZP66
Description
IC MCU 512K FLASH 66MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP66

Core Processor
PowerPC
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Freescale Semiconductor
buclk_enable = (STBUC | LOC) and LME lock indicates loss of lock status
bit (LOCS) for all cases and loss of clock sticky bit (LOCSS) when state 3
is active. When buclk_enable is changed, the chip asserts HRESET to
switch the system clock to BUCLK or PLL.
At PORESET negation, if the PLL is not locked, the loss-of-clock sticky bit
(LOCSS) is asserted, and the chip should operate with BUCLK.
buclk_enable = 1
& hreset_b = 0
else
3,BUCLK
6,BULCK
Figure 8-8. Clock Source Switching Flow Chart
MPC561/MPC563 Reference Manual, Rev. 1.2
poreset_b = 1
LME = 1
buclk_enable=0
& hreset_b=0
buclk_enable = 1
& hreset_b = 0
1,BUCLK
2,BUCLK
NOTE
else
5, osc
4, osc
LME = 0
buclk_enable = 0
& hreset_b = 0
hreset_b = 0
else
LOCS=0
Clocks and Power Control
8-15

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