MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 33

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

24.9.8
24.9.8.1
24.9.8.2
24.9.9
24.10
24.10.1
24.10.2
24.10.2.1
24.10.2.2
24.10.3
24.10.3.1
24.10.3.2
24.10.4
24.10.4.1
24.10.4.2
24.10.5
24.10.5.1
24.10.5.2
24.10.5.3
24.10.6
24.10.7
24.10.8
24.10.8.1
24.10.8.2
24.10.8.3
24.10.9
24.10.10
24.10.10.1
24.11
24.12
24.12.1
24.12.1.1
24.12.2
24.12.3
24.12.4
24.13
24.13.1
24.13.2
24.13.2.1
24.13.2.2
24.13.3
Freescale Semiconductor
Paragraph
Number
Read/Write Access ...................................................................................................... 24-59
Read/Write Timing Diagrams ..................................................................................... 24-69
Watchpoint Support ................................................................................................... 24-72
Ownership Trace ........................................................................................................ 24-74
Throughput and Latency ......................................................................................... 24-57
Data Timing Diagrams ............................................................................................ 24-57
Functional Description ............................................................................................ 24-59
Write Operation to Memory-Mapped Locations and SPR Registers ..................... 24-61
Read Operation to Memory-Mapped Locations and SPR Registers ...................... 24-63
Read/Write Access to Internal READI Registers ................................................... 24-64
Error Handling ........................................................................................................ 24-65
Exception Sequences .............................................................................................. 24-66
Secure Mode ........................................................................................................... 24-66
Error Messages ....................................................................................................... 24-66
Faster Read/Write Accesses with Default Attributes ............................................. 24-67
Throughput and Latency ......................................................................................... 24-68
Watchpoint Messaging ........................................................................................... 24-72
Watchpoint Overrun Error Message ....................................................................... 24-73
Synchronization ...................................................................................................... 24-74
Watchpoint Timing Diagrams ................................................................................ 24-74
Ownership Trace Messaging .................................................................................. 24-75
Queue Overflow Ownership Trace Error Message ................................................. 24-75
OTM Timing Diagrams .......................................................................................... 24-76
Assumptions for Throughput Analysis ............................................................... 24-57
Throughput Calculations .................................................................................... 24-57
Single Write Operation ....................................................................................... 24-61
Block Write Operation ........................................................................................ 24-62
Single Read Operation ........................................................................................ 24-63
Block Read Operation ......................................................................................... 24-64
Write Operation .................................................................................................. 24-64
Read Operation ................................................................................................... 24-65
Access Alignment ............................................................................................... 24-65
L-Bus Address Error ........................................................................................... 24-65
L-Bus Data Error ................................................................................................ 24-65
Read/Write Access Error .................................................................................... 24-66
Invalid Message .................................................................................................. 24-67
Invalid Access Opcode ....................................................................................... 24-67
Assumptions for Throughput Analysis ............................................................... 24-68
Watchpoint Source Field .................................................................................... 24-73
OTM Flow .......................................................................................................... 24-75
OTM Queueing ................................................................................................... 24-76
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Title
Number
Page
xxxiii