MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 357

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Refer to
Controller Option Registers
configuration bits.
9.5.4
The MPC561/MPC563 uses non-wrapping burst transfers to access operands of up to 32 bytes (eight
words). A non-wrapping burst access stops accessing the external device when the word address is modulo
four/eight. Burst configuration is determined by the value of BURST_EN in the SIUMCR register. See
Chapter 5, “Unified System Interface Unit (USIU)
begins the access by supplying a starting address that points to one of the words in the array and requires
the memory to sequentially drive or sample each word on the data bus. The selected slave device must
internally increment ADDR28 and ADDR29 (and ADDR30 in the case of a 16-bit port slave device, and
also ADDR31 in the case of an 8-bit port slave device) of the supplied address for each transfer, causing
the address to reach a four/eight word boundary, and then stop. The address and transfer attributes supplied
by the MPC561/MPC563 remain stable during the transfers. The selected device terminates each transfer
by driving or sampling the word on the data bus and asserting TA.
Freescale Semiconductor
CLKOUT
ADDR[8:31]
TS
RD/WR
TA
OE
Data
Figure 9-11. Read Followed by Write when Pre-Discharge Mode is Enabled, and EHTR is Set
Section 2.4, “Pad Module Configuration Register
Burst Transfer
Read Data
Read Cycle
(OR0–OR3),” for more information on PREDIS_EN, and EHTR
EHTR provides 1 clock
gap to three-state data bus
MPC561/MPC563 Reference Manual, Rev. 1.2
Overview” for further details. The MPC561/MPC563
Pre-discharge
to low voltage
(PDMCR2),” and
Write Cycle
Section 10.9.4, “Memory
Write Data
External Bus Interface
9-17