MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 400

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Memory Controller
Most memory controller features are common to all four banks. (For features unique to the CS0 bank, refer
to
bank is possible with 17 bits having address masking. The full 32-bit decode is available, even if all 32
address bits are not MPC561/MPC563 signals connected to the external device.
Each memory bank includes a variable block size of 32 Kbytes, 64 Kbytes and up to four Gbytes. Each
memory bank can be selected for read-only or read/write operation. The access to a memory bank can be
restricted to certain address type codes for system protection. The address type comparison occurs with a
mask option as well.
From 0 to 30 wait states can be programmed with TA generation. Four write-enable and byte-enable
signals (WE/BE[0:3]) are available for each byte that is written to memory. An output enable (OE) signal
is provided to eliminate external glue logic. A memory transfer start (MTS) strobe permits one master on
a bus to access external memory through the chip selects on another.
The memory controller functionality allows MPC561/MPC563-based systems to be built with little or no
glue logic. A minimal system using no glue logic is shown in
10-2
Section 10.7, “Global (Boot) Chip-Select
Internal Addresses [0:16], AT[0:2]
Base
Register
Base Register 3 (BR3)
Base Register (DMBR)
Dual Mapping
Figure 10-2. Memory Controller Block Diagram
Region Match Logic
MPC561/MPC563 Reference Manual, Rev. 1.2
0 (BR0)
1 (BR1)
2 (BR2)
Operation.”) A full 32-bit address decode for each memory
Option
Register
Wait State
Counter
Option Register 3 (OR3)
Option Register (DMOR)
Dual Mapping
Figure
Expired
Load
10-3. In this example CS0 is used for
Attributes
0 (OR0)
General-Purpose
1 (OR1)
2 (OR2)
Chip-Select
Machine
(GPCM)
Freescale Semiconductor
WE/BE[0:3]
CS[0:3]
OE