MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 442

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MPC564MZP66

Manufacturer Part Number
MPC564MZP66
Description
IC MCU 512K FLASH 66MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP66

Core Processor
PowerPC
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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L-Bus to U-Bus Interface (L2U)
When the access by the RCPU is not permitted, the L2U module asserts a data memory storage exception
to the RCPU.
For speculative load/store accesses from the RCPU to a region marked as guarded (G bit of region attribute
register is set), the L2U asks the RCPU to retry the L-bus cycle until either the access is not speculative,
or is canceled by the RCPU.
In the case of attempted accesses to a guarded region together with any other protection violation (no
access), the L2U retries the access. The L2U handles this event as a data storage violation only when the
access becomes non-speculative.
Note that access protection is active only when the MPC500’s MSR[DR] = 1. When MSR[DR] = 0, DMPU
exceptions are disabled, all accesses are considered to be to a guarded memory area, and no speculative
accesses are allowed. In this case, if the L-bus master [RCPU] initiates a non-CALRAM cycle (access
through the L2U) that is marked speculative, the L2U asks the RCPU to retry the L-bus cycle until either
the access is not speculative, or it is canceled by the RCPU Core.
11.5.2
Table 11-1
special purpose registers that are accessed via the MPC500 mtspr/mfspr instructions. The registers are also
accessed by an external master when EMCR[CONT] = 0. See
for register diagrams and bit descriptions.
11-6
.
shows registers that are used to control the DMPU of the L2U module. All the registers are
Associated Registers
The programmer must not overlap the CALRAM memory space with any
enabled region. Overlapping an enabled region with CALRAM memory
space disables the L2U data memory protection for that region.
If an enabled region overlaps with the L-bus space, the DMPU ignores all
accesses to addresses within the L-bus space. If an enabled region overlaps
with MPC500 register addresses, the DMPU ignores any access marked as
an MPC500 access.
L2U_RBA0
L2U_RBA1
L2U_RBA2
L2U_RBA3
L2U_GRA
L2U_RA0
L2U_RA1
L2U_RA2
L2U_RA3
Name
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 11-1. DMPU Registers
Region Base Address Register 0
Region Base Address Register 1
Region Base Address Register 2
Region Base Address Register 3
NOTE
Region Attribute Register 0
Region Attribute Register 1
Region Attribute Register 2
Region Attribute Register 3
Global Region Attribute
Description
Section 11.8, “L2U Programming
Freescale Semiconductor
Model,”

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