MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 450

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MPC564MZP66

Manufacturer Part Number
MPC564MZP66
Description
IC MCU 512K FLASH 66MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP66

Core Processor
PowerPC
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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L-Bus to U-Bus Interface (L2U)
11.8.4
The L2U region base address register (L2U_RBAx) defines the base address of a specific region protected
by the data memory protection unit. There are four registers (x = 0...3), one for each supported region.
11-14
Bits
3:31
1:2
Reset
Reset
Reset
Reset
0
Field
Field
Addr
Field
Field
Addr
Region Base Address Registers (L2U_RBAx)
MSB
SP
MSB
LSHOW
16
0
16
Name
0
SP
Undefined
17
LSHOW
1
17
1
RBA
Figure 11-5. L2U Region x Base Address Register (L2U_RBAx)
CALRAM Protection (SP) bit is used to protect the CALRAM on the L-bus from U-bus accesses.
Any attempt to set or clear the SP bit from the U-bus side has no affect.
Once this bit is set, the L2U blocks all CALRAM accesses initiated by the U-bus masters and the
access is terminated with a data error on the U-bus.
If L-bus show cycles are enabled, setting this bit will disable L-bus CALRAM show cycles.
LSHOW bits are used to configure the show cycle mode for cycles accessing the L-bus slave e.g.
CALRAM
00 Disable show cycles
01 Show address and data of all L-bus space write cycles
10 Reserved
11 Show address and data of all L-bus space read and write cycles
Reserved
Figure 11-4. L2U Module Configuration Register (L2U_MCR)
18
2
18
2
19
3
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 11-7. L2U_MCR Bit Descriptions
20
20
4
4
21
21
5
5
0000_0000_0000_0000
0000_0000_0000_0000
22
22
6
6
SPR 792–795
Undefined
23
SPR 568
23
7
7
RBA
Description
24
24
8
8
0000_0000_0000
25
25
9
9
10
26
10
26
11
27
11
27
12
28
12
28
Freescale Semiconductor
13
29
13
29
14
30
14
30
LSB
LSB
15
31
15
31

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