MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 488

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

QADC64E Legacy Mode Operation
13-24
10:15
Bits
6:9
5
Name
TOR2
CWP
QS
Queue 2 Trigger Overrun. TOR2 indicates that an unexpected trigger event has occurred
for queue 2. TOR2 can be set when queue 2 is in the active, suspended, and trigger
pending states.
The TOR2 trigger overrun can only occur when using an external trigger mode or a
periodic/interval timer mode. Trigger overruns cannot occur when the software initiated
single-scan mode and the software initiated continuous-scan mode are selected.
TOR2 occurs when a trigger event is received while queue 2 is executing, suspended, or
a trigger is pending. TOR2 has no effect on the queue execution. A trigger event that
causes a trigger overrun is not retained since it is considered unexpected.
An unexpected trigger event may be a system overrun situation, indicating a system
loading mismatch. The software acknowledges that it has detected a trigger overrun being
set by writing a zero to the trigger overrun, after the bit was read as a one. Once set, only
software or reset can clear TOR2.
0 No unexpected queue 2 trigger events have occurred
1 At least one unexpected queue 2 trigger event has occurred
Queue Status. The 4-bit read-only QS field indicates the current condition of queue 1 and
queue 2. The following are the five queue status conditions:
The two most significant bits are associated primarily with queue 1, and the remaining two
bits are associated with queue 2. Since the priority scheme between the two queues
causes the status to be interlinked, the status bits are considered as one 4-bit field.
Table 13-16
queue 2. Refer to
the 4-bit queue status field transitions in typical situations.
Command Word Pointer. The CWP allows the software to know which CCW is executing
at present, or was last completed. The command word pointer is a software read-only field,
and write operations have no effect. The CWP allows software to monitor the progress of
the QADC64E scan sequence. The CWP field is a CCW word pointer with a valid range of
0 to 63.
When a queue enters the paused state, the CWP points to the CCW with the pause bit set.
While in pause, the CWP value is maintained until a trigger event occurs on the same
queue or the other queue. Usually, the CWP is updated a few clock cycles before the queue
status field shows that the queue has become active. For example, software may read a
CWP pointing to a CCW in queue 2, and the status field shows queue 1 paused, queue 2
trigger pending.
When the QADC64E finishes the scan of the queue, the CWP points to the CCW where
the end-of-queue (EOQ) condition was detected. Therefore, when the end-of-queue
condition is a CCW with the EOQ code (channel 63), the CWP points to the CCW
containing the EOQ.
When the last CCW in a queue is in the last CCW table location (CCW63), and it does not
contain the EOQ code, the end-of-queue is detected when the following CCW is read, so
the CWP points to word CCW0.
Finally, when queue 1 operation is terminated after a CCW is read that is defined as BQ2,
the CWP points to the same CCW as BQ2.
During the stop mode, the CWP is reset to zero, since the control registers and the analog
logic are reset. When the freeze mode is entered, the CWP is unchanged; it points to the
last executed CCW.
• Idle
• Active
• Paused
• Suspended
• Trigger pending
Table 13-14. QASR0 Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
shows the bits in the QS field and how they affect the status of queue 1 and
Section 13.6, “Trigger and Queue Interaction
Description
Examples,” which shows
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