MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 49

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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Freescale Semiconductor
Figure
Number
QSPI Status Register (SPSR)................................................................................................ 15-21
QSPI RAM............................................................................................................................ 15-23
CR[0:F] — Command RAM 0x30 51C0, 0x30 51DF.......................................................... 15-24
Flowchart of QSPI Initialization Operation.......................................................................... 15-28
Flowchart of QSPI Master Operation (Part 1) ...................................................................... 15-29
Flowchart of QSPI Master Operation (Part 2) ...................................................................... 15-30
Flowchart of QSPI Master Operation (Part 3) ...................................................................... 15-31
Flowchart of QSPI Slave Operation (Part 1) ........................................................................ 15-32
Flowchart of QSPI Slave Operation (Part 2) ........................................................................ 15-33
SCI Transmitter Block Diagram ........................................................................................... 15-43
SCI Receiver Block Diagram ............................................................................................... 15-44
SCCxR0 — SCI Control Register 0 ..................................................................................... 15-46
SCI Control Register 1 (SCCxR1)........................................................................................ 15-47
SCIx Status Register (SCxSR).............................................................................................. 15-49
SCI Data Register (SCxDR) ................................................................................................. 15-51
Start Search Example............................................................................................................ 15-57
QSCI1 Control Register (QSCI1CR).................................................................................... 15-60
QSCI1 Status Register (QSCI1SR)....................................................................................... 15-61
Queue Transmitter Block Enhancements ............................................................................. 15-63
Queue Transmit Flow ........................................................................................................... 15-66
Queue Transmit Software Flow ............................................................................................ 15-66
Queue Transmit Example for 17 Data Bytes ........................................................................ 15-67
Queue Transmit Example for 25 Data Frames ..................................................................... 15-69
Queue Receiver Block Enhancements .................................................................................. 15-70
Queue Receive Flow ............................................................................................................. 15-73
Queue Receive Software Flow ............................................................................................. 15-74
Queue Receive Example for 17 Data Bytes.......................................................................... 15-75
TouCAN Block Diagram ........................................................................................................ 16-1
Typical CAN Network............................................................................................................ 16-3
Extended ID Message Buffer Structure .................................................................................. 16-4
Standard ID Message Buffer Structure ................................................................................... 16-4
Relationship between System Clock and CAN Bit Segments ................................................ 16-9
CAN Controller State Diagram............................................................................................. 16-12
Interrupt Levels on IRQ with ILBS ...................................................................................... 16-21
TouCAN Message Buffer Memory Map .............................................................................. 16-24
TouCAN Module Configuration Register (CANMCR) ....................................................... 16-25
TouCAN Interrupt Configuration Register (CANICR) ........................................................ 16-27
Control Register 0 (CANCTRL0)......................................................................................... 16-27
Control Register 1 (CANCTRL1)......................................................................................... 16-28
Prescaler Divide Register...................................................................................................... 16-29
MPC561/MPC563 Reference Manual, Rev. 1.2
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