MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 5

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.4.1
3.7.4.2
3.7.4.3
3.7.5
3.7.6
3.7.7
3.8
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9
3.9.10
3.9.10.1
3.9.10.2
3.9.10.3
3.10
3.10.1
3.10.2
3.10.3
3.11
3.11.1
3.11.2
3.11.3
3.11.4
3.11.5
3.12
3.13
3.13.1
3.13.2
Freescale Semiconductor
Paragraph
Number
User Instruction Set Architecture (UISA)
VEA Register Set — Time Base (TB) .......................................................................... 3-20
OEA Register Set .......................................................................................................... 3-20
Instruction Set ............................................................................................................... 3-27
Exception Model ........................................................................................................... 3-34
Instruction Timing ........................................................................................................ 3-37
User Instruction Set Architecture (UISA) .................................................................... 3-39
Register Set ............................................................................................................... 3-12
General-Purpose Registers (GPRs) ........................................................................... 3-12
Floating-Point Registers (FPRs) ............................................................................... 3-12
Floating-Point Status and Control Register (FPSCR) .............................................. 3-13
Condition Register (CR) ........................................................................................... 3-16
Integer Exception Register (XER) ............................................................................ 3-18
Link Register (LR) .................................................................................................... 3-19
Count Register (CTR) ............................................................................................... 3-19
Machine State Register (MSR) ................................................................................. 3-20
DAE/Source Instruction Service Register (DSISR) ................................................. 3-22
Data Address Register (DAR) .................................................................................. 3-23
Time Base Facility (TB) — OEA ............................................................................. 3-23
Decrementer Register (DEC) .................................................................................... 3-23
Machine Status Save/Restore Register 0 (SRR0) ..................................................... 3-23
Machine Status Save/Restore Register 1 (SRR1) ..................................................... 3-23
General SPRs (SPRG0–SPRG3) .............................................................................. 3-24
Processor Version Register (PVR) ........................................................................... 3-25
Implementation-Specific SPRs ................................................................................. 3-25
Instruction Set Summary .......................................................................................... 3-28
Recommended Simplified Mnemonics ..................................................................... 3-33
Calculating Effective Addresses ............................................................................... 3-34
Exception Classes ..................................................................................................... 3-35
Ordered Exceptions ................................................................................................... 3-35
Unordered Exceptions ............................................................................................... 3-35
Precise Exceptions .................................................................................................... 3-36
Exception Vector Table ............................................................................................ 3-36
Computation Modes .................................................................................................. 3-39
Reserved Fields ......................................................................................................... 3-39
Condition Register CR0 Field Definition ............................................................. 3-17
Condition Register CR1 Field Definition ............................................................. 3-17
Condition Register CRn Field — Compare Instruction ....................................... 3-17
EIE, EID, and NRI Special-Purpose Registers ..................................................... 3-25
Floating-Point Exception Cause Register (FPECR) ............................................. 3-26
Additional Implementation-Specific Registers ..................................................... 3-27
MPC561/MPC563 Reference Manual, Rev. 1.2
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