MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 569

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MPC564MZP66

Manufacturer Part Number
MPC564MZP66
Description
IC MCU 512K FLASH 66MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP66

Core Processor
PowerPC
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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A queue is in the active state when a valid queue operating mode is selected, when the selected trigger
event has occurred, or when the QADC64E is performing a conversion specified by a CCW from that
queue.
Only one queue can be active at a time. Either or both queues can be in the paused state. A queue is paused
when the previous CCW executed from that queue had the pause bit set. The QADC64E does not execute
any CCWs from the paused queue until a trigger event occurs. Consequently, the QADC64E can service
queue 2 while queue 1 is paused.
Only queue 2 can be in the suspended state. When a trigger event occurs on queue 1 while queue 2 is
executing, the current queue 2 conversion is aborted. The queue 2 status is reported as suspended. Queue
2 transitions back to the active state when queue 1 becomes idle or paused.
A trigger pending state is required since both queues cannot be active at the same time. The status of queue
2 is changed to trigger pending when a trigger event occurs for queue 2 while queue 1 is active. In the
opposite case, when a trigger event occurs for queue 1 while queue 2 is active, queue 2 is aborted and the
status is reported as queue 1 active, queue 2 suspended. So due to the priority scheme, only queue 2 can
be in the trigger pending state.
There are two transition cases which cause the queue 2 status to be trigger pending before queue 2 is shown
to be in the active state. When queue 1 is active and there is a trigger pending on queue 2, after queue 1
completes or pauses, queue 2 continues to be in the trigger pending state for a few clock cycles. The
following are fleeting status conditions:
Figure 14-13
transition from queue 1 active to queue 2 active.
The queue status field is affected by the stop mode. Since all of the analog logic and control registers are
reset, the queue status field is reset to queue 1 idle, queue 2 idle.
Freescale Semiconductor
Queue 1 idle with queue 2 trigger pending
Queue 1 paused with queue 2 trigger pending
displays the status conditions of the queue status field as the QADC64E goes through the
Idle (Paused)
Idle (Paused)
Queue 1
MPC561/MPC563 Reference Manual, Rev. 1.2
Active
Active
Figure 14-13. Queue Status Transition
Trigger Pending
Trigger Pending
Queue 2
Active
Idle
QADC64E Enhanced Mode Operation
QADC64E QUEUE STATUS
14-27

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