MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 594

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

QADC64E Enhanced Mode Operation
Byte access to an even address of a QADC64E location is shown in the top illustration of
the case of write cycles, byte 1 of the register is not disturbed. In the case of a read cycle, the QADC64E
provides both byte 0 and byte 1.
Byte access to an odd address of a QADC64E location is shown in the center illustration of
In the case of write cycles, byte 0 of the register is not disturbed. In the case of read cycles, the QADC64E
provides both byte 0 and byte 1.
16-bit accesses to an even address read or write byte 0 and byte 1 as shown in the lowest illustration of
Figure
16-bit accesses to an odd address require two bus cycles; one byte of two different 16-bit QADC64E
locations is accessed. The first bus cycle is treated by the QADC64E as an 8-bit read or write of an odd
address. The second cycle is an 8-bit read or write of an even address. The QADC64E address space is
organized into 16-bit even address locations, so a 16-bit read or write of an odd address obtains or provides
the lower half of one QADC64E location, and the upper half of the following QADC64E location.
14-52
14-24. The full 16 bits of data is written to and read from the QADC64E location with each access.
Intermodule Bus
Intermodule Bus
Intermodule Bus
QADC Location
QADC Location
QADC Location
8-bit Access of an Odd Address (ISIZ = 01, A0 = 1; OR ISIZ = 10, A0 = 1)
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 14-24. Bus Cycle Accesses
8-bit Access of an Even Address (ISIZ = 01, A0 = 0)
W
W
W
16-Bit Aligned Access (ISIZ = 10, A0 = 0)
Byte 0
Byte 0
Byte 0
Byte 0
BYTE 0
BYTE 0
R
R
R
W
W
W
Byte 1
Byte 1
Byte 1
Byte 1
BYTE 1
BYTE 1
R
R
R
QADC64E Bus CYC ACC
Freescale Semiconductor
Figure
Figure
14-24. In
14-24.