MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 60

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

G-11
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G-40
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G-42
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G-46
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G-50
lx
Figure
Number
Synchronous Output Signals Timing ..................................................................................... G-26
Synchronous Active Pull-Up And Open Drain Outputs Signals Timing .............................. G-27
Synchronous Input Signals Timing........................................................................................ G-28
Input Data Timing In Normal Case ....................................................................................... G-29
External Bus Read Timing (GPCM Controlled – ACS = ‘00’)............................................. G-30
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’)......................... G-31
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’)......................... G-32
External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’)... G-33
Address Show Cycle Bus Timing .......................................................................................... G-34
Address and Data Show Cycle Bus Timing........................................................................... G-35
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘0’) ...................... G-36
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘1’) ...................... G-37
External Bus Write Timing (GPCM Controlled – TRLX = ‘1’, CSNT = ‘1’) ...................... G-38
External Master Read From Internal Registers Timing......................................................... G-39
External Master Write To Internal Registers Timing ............................................................ G-40
Interrupt Detection Timing for External Edge Sensitive Lines ............................................. G-41
Debug Port Clock Input Timing ............................................................................................ G-42
Debug Port Timings............................................................................................................... G-42
Auxiliary Port Data Input Timing Diagram........................................................................... G-43
Auxiliary Port Data Output Timing Diagram ........................................................................ G-43
Enable Auxiliary From RSTI................................................................................................. G-44
Disable Auxiliary From RSTI................................................................................................ G-44
Reset Timing – Configuration from Data Bus....................................................................... G-45
Reset Timing – Data Bus Weak Drive During Configuration............................................... G-46
Reset Timing – Debug Port Configuration ............................................................................ G-47
JTAG Test Clock Input Timing ............................................................................................. G-48
JTAG Test Access Port Timing Diagram .............................................................................. G-48
Boundary Scan (JTAG) Timing Diagram.............................................................................. G-49
QSPI Timing – Master, CPHA = 0 ........................................................................................ G-54
QSPI Timing – Master, CPHA = 1 ........................................................................................ G-54
QSPI Timing – Slave, CPHA = 0 .......................................................................................... G-55
QSPI Timing – Slave, CPHA = 1 .......................................................................................... G-55
TPU3 Timing ......................................................................................................................... G-57
PPM_TCLK Timing .............................................................................................................. G-59
PPM Data Transfer Timing (SPI Mode)................................................................................ G-59
MCPSM Enable to VS_PCLK Pulse Timing Diagram ......................................................... G-60
MPWMSM Minimum Output Pulse Example Timing Diagram........................................... G-61
MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ............................. G-61
MPWMSM Enable To MPWMO Output Pin Rising Edge Timing Diagram ....................... G-62
MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram............. G-62
MPC561/MPC563 Reference Manual, Rev. 1.2
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