MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 605

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Recall QS = 0 => Queues disabled; QS = 8 => Q1 active, Q2 disabled; QS= 4 => Q1 paused, Q2 disabled.
A time separator was provided between the triggers and end of conversion (EOC). The relationship to
QCLK displayed is not guaranteed.
CWPQ1 or CWPQ2 typically lag CWP and only match CWP when the associated queue is inactive.
Another way to view CWPQ1(2) is that these registers update when EOC triggers the result register to be
written.
When the pause bit is set (CCW0), please note that CWP does not increment until triggered. When the
pause is not set (CCW1), the CWP increments with EOC.
The conversion results Q1 RES(x) show the result associated with CCW(x). So that R0 represents the
result associated with CCW0.
Example 2 below shows the timing for conversions in gated mode single-scan with the
same assumptions as example 1 except:
When the gate closes and opens again the conversions start with the first CCW in Q1.
When the gate closes the active conversion completes before the queue goes idle.
When Q1 completes both the CF1 bit sets and the SSE bit clears.
Freescale Semiconductor
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QCLK
Trig1
EOC
QS
CWP
CWPQ1
Q1 RES
Q1 RES shows relative result register updates
No pause bits set in any CCW
External trigger gated single-scan mode for Q1
Single-scan bit is set
LAST
0
Figure 14-44. External Trigger Mode (Positive Edge) Timing with Pause
LAST
4
8
MPC561/MPC563 Reference Manual, Rev. 1.2
CCW0
Conversion time is >= 14 QCLKS
Time between triggers
4
R0
CCW0
CCW1
QADC64E Enhanced Mode Operation
8
CCW1
R1
CCW2
14-63