MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 673

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MPC564MZP66

Manufacturer Part Number
MPC564MZP66
Description
IC MCU 512K FLASH 66MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP66

Core Processor
PowerPC
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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When TE is cleared, the transmitter is disabled after all pending idle, data, and break frames are
transmitted. The TC flag is set, and control of the TXD pin reverts to PQSPAR and DDRQS. Buffered data
is not transmitted after TE is cleared. To avoid losing data in the buffer, do not clear TE until TDRE is set.
Some serial communication systems require a mark on the TXD pin even when the transmitter is disabled.
Configure the TXD pin as an output, then write a one to either QDTX1 or QDTX2 of the PORTQS register.
See
pin, it reverts to driving a logic one output.
To insert a delimiter between two messages, to place non-listening receivers in wake-up mode between
transmissions, or to signal a re-transmission by forcing an idle-line, clear and then set TE before data in
the serial shifter has shifted out. The transmitter finishes the transmission, then sends a preamble. After the
preamble is transmitted, if TDRE is set, the transmitter marks idle. Otherwise, normal transmission of the
next sequence begins.
Both TDRE and TC have associated interrupts. The interrupts are enabled by the transmit interrupt enable
(TIE) and transmission complete interrupt enable (TCIE) bits in SCCxR1. Service routines can load the
last data frame in a sequence into SCxDR, then terminate the transmission when a TDRE interrupt occurs.
Two SCI messages can be separated with minimum idle time by using a preamble of 10 bit-times (11 if a
9-bit data format is specified) of marks (logic ones). Follow these steps:
In this sequence, if the first data frame of the second message is not transferred to TDRx prior to the finish
of the preamble transmission, then the transmit data line (TXDx pin) marks idle (logic one) until TDRx is
written. In addition, if the last data frame of the first message finishes shifting out (including the stop bit)
and TE is clear, TC goes high and transmission is considered complete. The TXDx pin reverts to being a
general-purpose output pin.
15.7.7.6
The receiver can be divided into two segments. The first is the receiver bit processor logic that
synchronizes to the asynchronous receive data and evaluates the logic sense of each bit in the serial stream.
The second receiver segment controls the functional operation and the interface to the CPU including the
conversion of the serial data stream to parallel access by the CPU.
15.7.7.7
The receiver bit processor contains logic to synchronize the bit-time of the incoming data and to evaluate
the logic sense of each bit. To accomplish this an RT clock, which is 16 times the baud rate, is used to
sample each bit. Each bit-time can thus be divided into 16 time periods called RT1–RT16. The receiver
Freescale Semiconductor
1. Write the last data frame of the first message to the TDRx
2. Wait for TDRE to go high, indicating that the last data frame is transferred to the transmit serial
3. Clear TE and then set TE back to one. This queues the preamble to follow the stop bit of the current
4. Write the first data frame of the second message to register TDRx
Section 15.5.1, “Port QS Data Register
shifter
transmission immediately.
Receiver Operation
Receiver Bit Processor
MPC561/MPC563 Reference Manual, Rev. 1.2
(PORTQS).” When the transmitter releases control of the TXD
Queued Serial Multi-Channel Module
15-55

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