MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 920

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Development Support
23.1.4.2
When using back trace, latching the value of the status pins (VF and VFLS), and the address of the cycles
marked as program trace cycle, should start immediately after the negation of reset. The start address is
the first address in the program trace cycle buffer.
When using window trace, latching the value of the status pins (VF and VFLS), and the address of the
cycles marked as program trace cycle, should start immediately after the first VSYNC is reported on the
VF pins. The start address of the trace window should be calculated according to first two VF pins reports.
Assuming that VF1 and VF2 are the two first VF pins reports and T1 and T2 are the two addresses of the
first two cycles marked with the program trace cycle attribute that were latched in the trace buffer, use the
following table to calculate the trace window start address.
23.1.4.3
Since the VF pins are used for reporting both instruction type information and queue flush information,
the external hardware must take special care when trying to detect the assertion/negation of VSYNC.
When VF = 011 it is a VSYNC assertion/negation report only if the previous VF pins value was one of the
following values: 000, 001, or 010.
23.1.4.4
The information on the status pins that describes the last fetched instruction and the last queue/history
buffer flushes, changes every clock. Cycles marked as program trace cycle are generated on the external
bus only when possible (when the SIU wins the arbitration over the external bus). Therefore, there is some
delay between the information reported on the status pins that a cycle marked as program trace cycle will
be performed on the external bus and the actual time that this cycle can be detected on the external bus.
When VSYNC is negated (through the serial interface of the development port), the CPU delays the report
of the of the assertion/negation of VSYNC on the VF pins (VF = 011) until all addresses marked with the
program trace cycle attribute were visible externally. Therefore, the external hardware should stop
23-6
11. Negate VSYNC
12. Return to the regular code run (issue an rfi). The first report on the VF pins is a VSYNC (VF = 011)
13. The external hardware stops sampling the program trace information upon the report on the VF
pins of VSYNC
VSYNC
VSYNC
VSYNC
VF1
011
011
011
Detecting the Trace Window Start Address
Detecting the Assertion/Negation of VSYNC
Detecting the Trace Window End Address
branch indirect taken
branch direct taken
sequential
VF2
001
110
101
Table 23-4. Detecting the Trace Buffer Start Point
MPC561/MPC563 Reference Manual, Rev. 1.2
Starting point
offset (T1 - 4)
T1 - 4 +
T1
T2
VSYNC asserted followed by a sequential instruction.
The start address is T1
VSYNC asserted followed by a taken direct branch.
The start address is the target of the direct branch
VSYNC asserted followed by a taken indirect branch.
The start address is the target of the indirect branch
Description
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