MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 923

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

23.2.1
This section describes the internal breakpoints and watchpoints support of the RCPU. For information on
external breakpoints support refer to
Internal breakpoint and watchpoint support is based on eight comparators comparing information on
instruction and load/store cycles, two counters, and two AND-OR logic structures. The comparators
perform compare on the Instruction address (I-address), on the load/store address (L-address) and on the
load/store data (L-data).
The comparators are able to detect the following conditions: equal, not equal, greater than, less than
(greater than or equal and less than or equal are easily obtained from these four conditions; for more
information refer to
structures “in range” and “out of range” detections (on address and on data) are supported. Using the
counters, it is possible to program a breakpoint to be recognized after an event was detected a predefined
number of times.
The L-data comparators can operate on fix point data of load or store. When operating on fix point data
the L-data comparators are able to perform compare on bytes, half-words and words and can treat numbers
either as signed or as unsigned values.
Freescale Semiconductor
Internal
Watchpoints
Logic
Development
Port
Development
System OR
External
Peripherals
LCTRL2
MSR
X
X
Internal Watchpoints and Breakpoints
(Non-masked Control Bit)
Non-maskable Breakpoint
MSR[RI]
Maskable Breakpoint
Development Port Trap Enable Bits
Software trap Enable Bits
bit wise AND
bit wise OR
Watchpoints
Section 23.2.1.6, “Generating Six Compare
Figure 23-1. Watchpoint and Breakpoint Support in the CPU
Internal
Peripherals
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 23.3, “Development System
X
Counters
Types”). Using the AND-OR logic
X
Interface.”
To Watchpoint
Pins
Breakpoint
to CPU
Development Support
23-9