C8051F021 Silicon Laboratories Inc, C8051F021 Datasheet - Page 202

• Manufacturer Part Number: C8051F021
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F02xr

Specifications of C8051F021

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F020/1/2/3
202
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SPIF
R/W
Bit7
SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this
bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared
by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0
data register was attempted while a data transfer was in progress. If interrupts are enabled, setting this
bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared
by hardware. It must be cleared by software.
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is
detected (NSS is low and MSTEN = 1). If interrupts are enabled, setting this bit causes the CPU to
vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must
be cleared by software.
RXOVRN: Receive Overrun Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still
holds unread data from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 inter-
rupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software.
TXBSY: Transmit Busy Flag.
This bit is set to logic 1 by hardware while a master mode transfer is in progress. It is cleared by hard-
ware at the end of the transfer.
SLVSEL: Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating it is enabled as a slave. It is cleared to
logic 0 when NSS is high (slave disabled).
MSTEN: Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
WCOL
R/W
Bit6
MODF
Figure 19.6. SPI0CN: SPI0 Control Register
R/W
Bit5
RXOVRN
R/W
Bit4
Rev. 1.4
TXBSY
Bit3
R
SLVSEL
Bit2
R
MSTEN
R/W
Bit1
(bit addressable)
SPIEN
R/W
Bit0
SFR Address:
00000000
Reset Value
0xF8