C8051F021 Silicon Laboratories Inc, C8051F021 Datasheet - Page 230

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C8051F021

Manufacturer Part Number
C8051F021
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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C8051F020/1/2/3
22.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
Timer 0 and Timer 1 behave differently in Mode 3. Timer 0 is configured as two separate 8-bit counter/timers held in
TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD:
TR0, C/T0, GATE0 and TF0. It can use either the system clock or an external input signal as its timebase. The timer
in the TH0 register is restricted to a timer function sourced by the system clock. TH0 is enabled using the Timer 1 run
control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt.
Timer 1 is inactive in Mode 3, so with Timer 0 in Mode 3, Timer 1 can be turned off and on by switching it into and
out of its Mode 3. When Timer 0 is in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked by
external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to gener-
ate the baud clock for UART0 and/or UART1. Refer to
“21. UART1” on page 215
230
SYSCLK
/INT0
T0
Crossbar
Figure 22.4. T0 Mode 3 (Two 8-bit Timers) Block Diagram
GATE0
12
for information on configuring Timer 1 for baud rate generation.
0
1
M
T
4
TR0
CKCON
M
T
2
0
1
M
T
1
M
T
0
Rev. 1.4
TR1
G
A
T
E
1
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
G
A
T
E
0
Section “20. UART0” on page 205
C
T
0
/
M
T
0
1
M
T
0
0
(8 bits)
(8 bits)
TH0
TL0
TR1
TR0
TF1
TF0
IE1
IT1
IE0
IT0
and
Interrupt
Interrupt
Section

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