C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 107

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.
On-chip, re-programmable FLASH memory is included for program code and non-volatile data storage. The FLASH
memory can be programmed in-system, a single byte at a time, through the C2 interface or by software using the
MOVX instruction. Once cleared to logic 0, a FLASH bit must be erased to set it back to logic 1. FLASH bytes would
typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automatically timed
by hardware for proper execution; data polling to determine the end of the write/erase operation is not required. Code
execution is stalled during a FLASH write/erase operation. Refer to Table 11.1 for complete FLASH memory electri-
cal characteristics.
11.1.
The simplest means of programming the FLASH memory is through the C2 interface using programming tools pro-
vided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For
details on the C2 commands to program FLASH memory, see
To ensure the integrity of FLASH contents, it is strongly recommended that the on-chip VDD Monitor be
enabled in any system that includes code that writes and/or erases FLASH memory from software.
11.1.1. FLASH Lock and Key Functions
FLASH writes and erases by user software are protected with a lock and key function. The FLASH Lock and Key
Register (FLKEY) must be written with the correct key codes, in sequence, before FLASH operations may be per-
formed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be written in order. If the key
codes are written out of order, or the wrong codes are written, FLASH writes and erases will be disabled until the next
system reset. FLASH writes and erases will also be disabled if a FLASH write or erase is attempted before the key
codes have been written properly. The FLASH lock resets after each write or erase; the key codes must be written
again before a following FLASH operation can be performed. The FLKEY register is detailed in Figure 11.3.
11.1.2. FLASH Erase Procedure
The FLASH memory can be programmed by software using the MOVX write instruction with the address and data
byte to be programmed provided as normal operands. Before writing to FLASH memory using MOVX, FLASH write
operations must be enabled by: (1) Writing the FLASH key codes in sequence to the FLASH Lock register (FLKEY);
and (2) Setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to tar-
get FLASH memory). The PSWE bit remains set until cleared by software.
A write to FLASH memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic
1 in FLASH. A byte location to be programmed must be erased before a new value is written. The FLASH mem-
ory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in the page to
0xFF). To erase an entire 512-byte page, perform the following steps:
FLASH MEMORY
Programming The FLASH Memory
Step 1. Disable interrupts (recommended).
Step 2. Write the first key code to FLKEY: 0xA5.
Step 3. Write the second key code to FLKEY: 0xF1.
Step 4. Set the PSEE bit (register PSCTL).
Step 5. Set the PSWE bit (register PSCTL).
Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be
Step 7. Clear the PSWE bit (register PSCTL).
Step 8. Clear the PSEE bit (register PSCTI).
erased.
Rev. 1.1
Section “21. C2 Interface” on page
C8051F320/1
253.
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