C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 127

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.
Digital and analog resources are available through 25 I/O pins (C8051F320) or 21 I/O pins (C8051F321). Port pins
are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog
input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as shown in Figure 14.3. The
designer has complete control over which functions are assigned, limited only by the number of physical I/O pins.
This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of
a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 14.3
and Figure 14.4). The registers XBR0 and XBR1, defined in Figure 14.5 and Figure 14.6, are used to select internal
digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured as either
push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3). Complete Electrical Spec-
ifications for Port I/O are given in Table 14.1 on page 142.
Highest
Priority
Lowest
Priority
PORT INPUT/OUTPUT
SYSCLK
Outputs
Outputs
SMBus
T0, T1
UART
P0
P1
P2
P3
CP0
CP1
PCA
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
Figure 14.1. Port I/O Functional Block Diagram
(P3.0)
2
4
2
2
2
6
2
8
8
8
8
PnSKIP Registers
XBR0, XBR1,
Crossbar
Rev. 1.1
Decoder
Priority
Digital
8
8
8
1
PnMDIN Registers
PnMDOUT,
Cells
Cells
Cells
Cells
Note: P2.4-P2.7 only available
I/O
I/O
I/O
I/O
P0
P1
P2
P3
on the C8051F320
C8051F320/1
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
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