C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 131

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.2. Port I/O Initialization
Port I/O initialization consists of the following steps:
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs
should be configured as an analog inputs. When a pin is configured as an analog input, its weak pull-up, digital driver,
and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins configured as
digital inputs may still be used by analog peripherals; however this practice is not recommended. To configure a Port
pin for digital input, write ‘0’ to the corresponding bit in register PnMDOUT, and write ‘1’ to the corresponding Port
latch (register Pn).
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by setting the
associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates a digital input, and a
‘0’ indicates an analog input. All pins default to digital inputs on reset. See Figure 14.8 for the PnMDIN register
details.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each
Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital
resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL)
pins, which are configured as open-drain regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is
‘0’, a weak pull-up is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull
Port I/O. Furthermore, the weak pull-up is turned off on an output that is driving a ‘0’ to avoid unnecessary power
dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions required by
the design. Setting the XBARE bit in XBR1 to ‘1’ enables the Crossbar. Until the Crossbar is enabled, the external
pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register
settings, one can determine the I/O pin-out using the Priority Decode Table; as an alternative, the Configuration Wiz-
ard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register
settings.
Important Note: The Crossbar must be enabled to use Ports P0, P1, and P2.0-P2.3 as standard Port I/O in output
mode. These Port output drivers are disabled while the Crossbar is disabled. P2.4-P2.7 and P3.0 always function as
standard GPIO.
Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register
Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode
Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
Step 4. Assign Port pins to desired peripherals (XBR0, XBR1).
Step 5. Enable the Crossbar (XBARE = ‘1’).
(PnMDIN).
register (PnMDOUT).
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