C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 162

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a
STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit will be set to ‘1’
and an interrupt generated. The following conditions will cause hardware to generate a STALL condition:
Firmware sets the SDSTL bit (E0CSR.5) to ‘1’.
15.10.1.Endpoint0 SETUP Transactions
All control transfers must begin with a SETUP packet. SETUP packets are similar to OUT packets, containing an
8-byte data field sent by the host. Any SETUP packet containing a command field of anything other than 8 bytes will
be automatically rejected by USB0. An Endpoint0 interrupt is generated when the data from a SETUP packet is
loaded into the Endpoint0 FIFO. Software should unload the command from the Endpoint0 FIFO, decode the com-
mand, perform any necessary tasks, and set the SOPRDY bit to indicate that it has serviced the OUT packet.
15.10.2.Endpoint0 IN Transactions
When a SETUP request is received that requires USB0 to transmit data to the host, one or more IN requests will be
sent by the host. For the first IN transaction, firmware should load an IN packet into the Endpoint0 FIFO, and set the
INPRDY bit (E0CSR.1). An interrupt will be generated when an IN packet is transmitted successfully. Note that no
interrupt will be generated if an IN request is received before firmware has loaded a packet into the Endpoint0 FIFO.
If the requested data exceeds the maximum packet size for Endpoint0 (as reported to the host), the data should be split
into multiple packets; each packet should be of the maximum packet size excluding the last (residual) packet. If the
requested data is an integer multiple of the maximum packet size for Endpoint0, the last data packet should be a
zero-length packet signaling the end of the transfer. Firmware should set the DATAEND bit to ‘1’ after loading into
the Endpoint0 FIFO the last data packet for a transfer.
Upon reception of the first IN token for a particular control transfer, Endpoint0 is said to be in Transmit Mode. In this
mode, only IN tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is set to ‘1’ if a SETUP or
OUT token is received while Endpoint0 is in Transmit Mode.
Endpoint0 will remain in Transmit Mode until any of the following occur:
Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when performing (2) and (3) above.
The SIE will transmit a NAK in response to an IN token if there is no packet ready in the IN FIFO (INPRDY = ‘0’).
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The host sends an OUT token during a OUT data phase after the DATAEND bit has been set to ‘1’.
The host sends an IN token during an IN data phase after the DATAEND bit has been set to ‘1’.
The host sends a packet that exceeds the maximum packet size for Endpoint0.
The host sends a non-zero length DATA1 packet during the status phase of an IN transaction.
USB0 receives an Endpoint0 SETUP or OUT token.
Firmware sends a packet less than the maximum Endpoint0 packet size.
Firmware sends a zero-length packet.
Rev. 1.1