C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 166

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
15.11. Configuring Endpoints1-3
Endpoints1-3 are configured and controlled through their own sets of the following control/status registers: IN regis-
ters EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of endpoint control/
status registers is mapped into the USB register address space at a time, defined by the contents of the INDEX regis-
ter (Figure 15.6).
Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in
point mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH.
When SPLIT = ‘1’, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available.
When SPLIT = ‘0’, the corresponding endpoint functions as either IN or OUT; the endpoint direction is selected by
the DIRSEL bit in register EINCSRH.
15.12. Controlling Endpoints1-3 IN
Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used for Inter-
rupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in register
EINCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 IN interrupt is generated by any of the following conditions:
15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode
When the ISO bit (EINCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt Mode. Once an endpoint has
been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_INTERFACE com-
mand), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY bit (EINCSRL.0). Upon
reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and generate an interrupt.
Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be transmit-
ted upon reception of the next IN token.
A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EINCSRL.4). While
SDSTL = ‘1’, hardware will respond to all IN requests with a STALL condition. Each time hardware generates a
STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to ‘1’. The STSTL bit must be
reset to ‘0’ by firmware.
Hardware will automatically reset INPRDY to ‘0’ when a packet slot is open in the endpoint FIFO. Note that if dou-
ble buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO at a
time. In this case, hardware will reset INPRDY to ‘0’ immediately after firmware loads the first packet into the FIFO
and sets INPRDY to ‘1’. An interrupt will not be generated in this case; an interrupt will only be generated when a
data packet is transmitted.
When firmware writes ‘1’ to the FCDT bit (EINCSRH.3), the data toggle for each IN packet will be toggled continu-
ously, regardless of the handshake received from the host. This feature is typically used by Interrupt endpoints func-
tioning as rate feedback communication for Isochronous endpoints. When FCDT = ‘0’, the data toggle bit will only
be toggled when an ACK is sent from the host in response to an IN packet.
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1.
2.
3.
An IN packet is successfully transferred to the host.
Software writes ‘1’ to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty.
Hardware generates a STALL condition.
Rev. 1.1
Section
15.5.1. The end-