C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 179

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial
transfers; higher level protocol is determined by user software. The SMBus interface provides the following applica-
tion-independent features:
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SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting, this inter-
rupt is generated after the ACK cycle so that software may read the received ACK value; when receiving data, this
interrupt is generated before the ACK cycle so that software may define the outgoing ACK value. See
“16.5. SMBus Transfer Modes” on page 187
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or the end of a
transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control register) to find the
cause of the SMBus interrupt. The SMB0CN register is described in
on page
SMBus configuration options include:
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These options are selected in the SMB0CF register, as described in
ter” on page
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Timeout detection (SCL Low Timeout and/or Bus Free Timeout)
SDA setup and hold time extensions
Slave event enable/disable
Clock source selection
183; Table 16.4 provides a quick SMB0CN decoding reference.
180.
for more details on transmission sequences.
Rev. 1.1
Section “16.4.1. SMBus Configuration Regis-
Section “16.4.2. SMB0CN Control Register”
C8051F320/1
Section
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