C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 180

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
16.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the
SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is
enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhib-
ited, the SMBus interface will still monitor the SCL and SDA pins; however, the interface will NACK all received
addresses and will not generate any slave interrupts. When the INH bit is set, all slave events will be inhibited follow-
ing the next START (interrupts will continue for the duration of the current transfer).
The SMBCS1-0 bits select the SMBus clock source, which is used only when operating as a master or when the Free
Timeout detection is enabled. When operating as a master, overflows from the selected source determine the absolute
minimum SCL low and high times as defined in Equation 16.1. Note that the selected clock source may be shared by
other peripherals so long as the timer is left running at all times. For example, Timer 1 overflows may generate the
SMBus and UART baud rates simultaneously. Timer configuration is covered in
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 16.1. When the interface is operating as a master (and SCL is not driven or extended by any other devices
on the bus), the typical SMBus bit rate is approximated by Equation 16.2.
180
Equation 16.1. Minimum SCL High and Low Times
SMBCS1 SMBCS0 SMBus Clock Source
T
Table 16.1. SMBus Clock Source Selection
HighMin
Equation 16.2. Typical SMBus Bit Rate
0
0
1
1
BitRate
=
T
0
1
0
1
LowMin
=
f
--------------------------------------------- -
ClockSourceOverflow
Rev. 1.1
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
=
--------------------------------------------- -
f
ClockSourceOverflow
Timer 0 Overflow
Timer 1 Overflow
3
1
Section “19. Timers” on page
217.