C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 186

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C8051F320

Manufacturer Part Number
C8051F320
Description
IC 8051 MCU 16K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheet

Specifications of C8051F320

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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C8051F320/1
16.4.3. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received.
Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access
the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the
process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is
located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in.
SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from
master transmitter to slave receiver is made with the correct data or address in SMB0DAT.
186
Bits7-0:
R/W
Bit7
SMB0DAT: SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a
byte that has just been received on the SMBus serial interface. The CPU can read from or write to this
register whenever the SI serial interrupt flag (SMB0CN.0) is set to logic 1. The serial data in the reg-
ister remains stable as long as the SI flag is set. When the SI flag is not set, the system may be in the
process of shifting data in/out and the CPU should not attempt to access this register.
R/W
Bit6
Figure 16.7. SMB0DAT: SMBus Data Register
R/W
Bit5
R/W
Bit4
Rev. 1.1
R/W
Bit3
R/W
Bit2
R/W
Bit1
SFR Address:
R/W
Bit0
0xC2
00000000
Reset Value

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