C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 193

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced
baud rate support allows a wide range of clock sources to generate standard baud rates (details in
“17.1. Enhanced Baud Rate Generation” on page
of a second incoming data byte before software has finished reading the previous data byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0). The single
SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0 always access the Trans-
mit register. Reads of SBUF0 always access the buffered Receive register; it is not possible to read data from
the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in SCON0), or
a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not cleared by hardware when
the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to
determine the cause of the UART0 interrupt (transmit complete or receive complete).
UART0
Rate Generator
UART Baud
Write to
SBUF
Figure 17.1. UART0 Block Diagram
Rx Clock
Tx Clock
Stop Bit
Start
Start
SBUF
Read
SCON
D
TB8
SET
CLR
Shift
Input Shift Register
Q
Shift
SFR Bus
(RX Latch)
Rx Control
(9 bits)
Tx Control
SBUF
0x1FF
SFR Bus
Zero Detector
(TX Shift)
SBUF
194). Received data buffering allows UART0 to start reception
RB8
Load SBUF
Tx IRQ
Rx IRQ
Rev. 1.1
TI
RI
SBUF
Load
Send
Data
Interrupt
Serial
Port
TX
RX
Crossbar
Crossbar
C8051F320/1
Port I/O
Section
193