C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 211

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bits 3-2: NSSMD1-NSSMD0: Slave Select Mode.
Bit 1:
Bit 0:
SPIF
R/W
Bit7
SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this
bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared
by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0
data register was attempted while a data transfer was in progress. It must be cleared by software.
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is
detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by
hardware. It must be cleared by software.
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still
holds unread data from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. This bit is not automatically cleared by hardware. It must be cleared by software.
Selects between the following NSS operation modes:
(See
Mode Operation” on page
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will assume
the value of NSSMD0.
TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the
transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is
safe to write a new byte to the transmit buffer.
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
WCOL
Section “18.2. SPI0 Master Mode Operation” on page 205
R/W
Bit6
MODF
Figure 18.9. SPI0CN: SPI0 Control Register
R/W
Bit5
RXOVRN NSSMD1
207).
R/W
Bit4
R/W
Bit3
Rev. 1.1
NSSMD0
R/W
Bit2
TXBMT
and
Bit1
R
Section “18.3. SPI0 Slave
C8051F320/1
SFR Address: 0xF8
SPIEN
R/W
Bit0
00000110
Addressable
Reset Value
Bit
211