C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 218

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal /INT0 is
active as defined by bit IN0PL in register INT01CF (see Figure 8.13). Setting GATE0 to ‘1’ allows the timer to be
controlled by the external input signal /INT0 (see
facilitating pulse width measurements.
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial value before
the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1
is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal /INT1 is
used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register INT01CF (see Figure 8.13).
19.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are
enabled and configured in Mode 1 in the same manner as for Mode 0.
218
/INT0
TR0
T0
X = Don't Care
0
1
1
1
Crossbar
GATE0
Pre-scaled Clock
X
0
1
1
SYSCLK
IN0PL
GATE0
/INT0
XOR
X
X
0
1
Figure 19.1. T0 Mode 0 Block Diagram
TR0
0
1
Counter/Timer
M
H
T
3
M
T
3
L
CKCON
M
H
T
2
Disabled
Disabled
Enabled
Enabled
M
T
2
L
0
1
M
T
1
M
T
0
Section “8.3.5. Interrupt Register Descriptions” on page
S
C
A
1
S
C
A
Rev. 1.1
0
G
A
T
E
1
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
N
1
P
L
I
N
S
1
L
2
I
INT01CF
N
S
1
L
1
I
N
S
1
L
0
I
N
P
0
L
I
(8 bits)
TH0
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
I
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
Interrupt
61),