MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet
MC56F8323VFB60
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MC56F8323VFB60 Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8323 Rev. 17 04/2007 freescale.com ...
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... Table 10-3 and Table 11-1; added note to Vcap pin in 4-12; removed unneccessary notes in 10-14; added ADC calibration information to Table 10-1. Table . Table 10-1; also removed overall life in Table D Table 10-4. Added new Freescale Semiconductor 10-5. in Part 2-2, 10-3. Preliminary ...
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... For normal operation, connect TRST directly to V environment, TRST may be tied to V Rev. 17 Changed the “Frequency Accuracy” specification in Please see http://www.freescale.com for the most current data sheet revision. Freescale Semiconductor Preliminary Document Revision History Description of Change Table 2-2. Clarified external reference crystal Table 10-14 by increasing maximum value to 8 ...
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... Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... SCI0 or Decoding GPIOC Peripherals FlexCAN or 2 GPIOC Freescale Semiconductor Preliminary • One Quadrature Decoder • One FlexCAN module • two Serial Communication Interfaces (SCIs) • two Serial Peripheral Interfaces (SPIs) • Two general-purpose Quad Timers • Computer Operating Properly (COP)/Watchdog • ...
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... Thermal Design Considerations . . . . . . . 136 12.2. Electrical Design Considerations . . . . . . . 137 12.3. Power Distribution and I/O Ring Part 13: Ordering Information . . . . . . . . . . 139 56F8323 Technical Data, Rev. 17 Interrupt Timing . . . . . . . . . . . . . 117 (SCI) Timing . . . . . . . . . . . . . . . . 123 (ADC) Parameters . . . . . . . . . . . 126 Information . . . . . . . . . . . . . . . . . . 131 Information . . . . . . . . . . . . . . . . . 133 Implementation . . . . . . . . . . . . . . 138 Freescale Semiconductor Preliminary ...
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... Differences Between Devices Table 1-1 outlines the key differences between the 56F8323 and 56F8123 devices. Feature Guaranteed Speed Program RAM Data Flash PWM CAN Quadrature Decoder Temperature Sensor Dedicated GPIO Freescale Semiconductor Preliminary Table 1-1 Device Differences 56F8323 60MHz/60 MIPS 4KB 8KB — ...
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... General Purpose I/O (GPIO) pins • Integrated Power-On Reset and Low-Voltage Interrupt Module • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent, real-time debugging • Software-programmable, Phase Lock Loop (PLL) • On-chip relaxation oscillator 8 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned Freescale Semiconductor Preliminary 56F8323 Technical Data, Rev. 17 ...
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... A complete set of evaluation modules (EVMs), demonstration board kit and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 10 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... C, Channel 2, input as indicated. The timer can then be used to introduce a controllable delay before generating its output signal. The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals. Freescale Semiconductor Preliminary Figure 1-1 and ...
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... The primary data RAM port is 32 bits wide. Other data ports are 12 pdb_m[15:0] pab[20:0] cdbw[31:0] xab1[23:0] xab2[23:0] Figure 1-1 System Bus Interfaces 56F8323 Technical Data, Rev. 17 Boot Flash Program Flash Program RAM Data RAM Data Flash To Flash Control IPBus Logic Bridge Flash Memory Module IPBus 16 bits. Freescale Semiconductor Preliminary ...
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... CLKGEN (OSC/PLL) (ROSC) Timer A 4 Quadrature Decoder 0 2 FlexCAN 4 2 NOT available on the 56F8123 device. Freescale Semiconductor Preliminary To/From IPBus Bridge SCI 1 SPI 0 GPIO A GPIO B GPIO C IPBus Figure 1-2 Peripheral Subsystem 56F8323 Technical Data, Rev. 17 Architecture Block Diagram Interrupt Controller Low-Voltage Interrupt POR & ...
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... Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced Table 1-2 Bus Signal Names Function Program Memory Interface Primary Data Memory Interface Bus 1 , words, and long data types. Data is written Secondary Data Memory Interface Peripheral Interface Bus 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... Examples: Signal/Symbol PIN PIN PIN PIN 1. Values for and Freescale Semiconductor Preliminary are required for a complete description and proper design with the Freescale Literature Distribution Table 1-3 Chip Documentation Description Logic State True False True False are defined by individual product specifications. ...
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... Table 1-1 for 56F8123 functional differences. 16 Figure 2-1 and Figure 2-2. In 56F8323 3 4 pins serve as 2.5V V power inputs CAP DD_CORE 56F8323 Technical Data, Rev. 17 Table 2-2, each table row Number of Pins in Package 56F8123 — — 2 — — — — 10 Freescale Semiconductor Preliminary ...
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... Power V DDA_OSC_PLL Power Ground V Power V Ground Other CAP Supply OCR_DIS Ports EXTAL (GPIOC0) PLL and Clock or XTAL (GPIOC1) GPIO JTAG/ EOnCE Port Figure 2-1 56F8323 Signals Identified by Functional Group (64-Pin LQFP) Freescale Semiconductor Preliminary V DD_IO DDA_ADC 1 1 SSA_ADC CAP 56F8323 TCK ...
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... SS0 (TXD1, GPIOB0) GPIOA0-1 SS1 (GPIOA2) MISO1 (GPIOA3) SPI1 or MOSI1 (GPIOA4) GPIO SCLK1 (GPIOA5) GPIOA6-8 GPIOA9-11 ANA0 - 7 ADCA V REF GPIOC2 GPIO GPIOC3 TC0 (TXD0, GPIOC6) QUAD TC1 (RXD0, GPIOC5) TIMER C or SCI0 or GPIO TC3 (GPIOC4) IRQA (V ) INTERRUPT/ PP PROGRAM RESET CONTROL Freescale Semiconductor Preliminary ...
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... Supply SSA_ADC Freescale Semiconductor Preliminary Table 2-2. Any alternate functionality must be programmed. State During Reset I/O Power — This pin supplies 3.3V power to the chip I/O interface and also the Processor core throught the on-chip voltage regulator enabled. Oscillator and PLL Power — This pin supplies 3.3V power to the OSC and to the internal regulator that in turn supplies the Phase Locked Loop ...
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... JTAG/EOnCE internally port. The pin is connected internally to a pull-down resistor. A Schmitt trigger input is used for noise immunity. 56F8323 Technical Data, Rev. 17 Signal Description (regulator enabled (regulator disabled), these pins Freescale Semiconductor Preliminary ...
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... Input/ Output (GPIOB7) Schmitt Input/ Output (oscillator_ Output clock) Freescale Semiconductor Preliminary State During Reset Input, Test Mode Select Input — This input pin is used to sequence the pulled high JTAG TAP controller’s state machine sampled on the rising internally edge of TCK and has an on-chip pull-up resistor. ...
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... Clock Output - can be used to monitor the internal SYS_CLK signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR). In the 56F8323, the default state after reset is INDEX0. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. 56F8323 Technical Data, Rev. 17 Signal Description Freescale Semiconductor Preliminary ...
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... Output MOSI0 24 Schmitt Input/ Output (GPIOB2) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Reset Input, Home — Quadrature Decoder 0, HOME input pull-up enabled TA3 — Timer A, Channel 3 Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ...
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... Port A GPIO — This GPIO pin can be individually programmed as pull- input or output pin. enabled In the 56F8323, the default state after reset is PWMA1. In the 56F8123, the default state is not one of the functions offered and must be reconfigured 56F8323 Technical Data, Rev. 17 Signal Description Freescale Semiconductor Preliminary ...
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... Output (MOSI1) Schmitt Input/ Output (GPIOA4) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Reset In reset, PWMA2 — This is one of six PWMA output pins. output is disabled, SPI 1 Slave Select — SS1 is used in slave mode to indicate to the pull-up is SPI module that the current transfer received. ...
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... Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is FAULTA2. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. 56F8323 Technical Data, Rev. 17 Signal Description Freescale Semiconductor Preliminary ...
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... ANA6 32 ANA7 Schmitt REFH Input Freescale Semiconductor Preliminary State During Reset Input, ISA0 — This input current status pin is used for top/bottom pulse pull-up width correction in complementary channel operation for PWMA. enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin ...
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... Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is CAN_TX. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. 56F8323 Technical Data, Rev. 17 Signal Description — Internal pins for voltage reference which . SS Freescale Semiconductor Preliminary ...
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... Schmitt Input (V ) Input PP RESET 2 Schmitt Input Freescale Semiconductor Preliminary State During Reset Input, TC0 — Timer C, Channel 0 pull-up enabled Transmit Data — SCI0 transmit data output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TC0. ...
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... The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins. 30 Table 10-15. A recommended crystal oscillator circuit is shown EXTAL XTAL Sample External Crystal Parameters 750 KΩ Note: If the operating temperature range is limited to o below 85 CL2 56F8323 Technical Data, Rev Meg Ω C (105 C junction), then R z Figure Freescale Semiconductor 3-2. Preliminary ...
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... To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.1% of 8MHz by trimming an internal capacitor. Bits 0-9 of the OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset value Freescale Semiconductor Preliminary 3 Terminal ...
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... Lock Detector Reference Detector Figure 3-4 Internal Clock Operation 56F8323 Technical Data, Rev. 17 ZSRC SYS_CLK2 source to the SIM PLLCOD /2 Postscaler OUT Postscaler CLK ÷ ( Bus Interface Bus & Control Interface LCK Loss of loss of reference clock interrupt Clock Freescale Semiconductor Preliminary ...
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... EMI, the OMR MA bit, which is used to decide internal or external BOOT, will have no effect on the Program Memory Map. OMR MB reflects the security status of the Program Flash. After reset, changing the OMR MB bit will have no effect on the Program Flash. Freescale Semiconductor Preliminary Table Table 4-1 ...
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... Cop Reset Address = $02 0002 Boot Location = $02 0000 RESERVED Internal Program Flash 32KB Vector Base Address + Reserved for Reset Overlay Reserved for COP Reset Overlay P:$04 Illegal Instruction P:$06 SW Interrupt 3 56F8323 Technical Data, Rev. 17 Part 5.6.11 1 Interrupt Function 2 2 Freescale Semiconductor Preliminary ...
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... SPI1 39 0-2 SPI0 40 0-2 SPI0 41 0-2 SCI1 42 0-2 SCI1 43 0-2 Freescale Semiconductor Preliminary Vector Base Address + P:$08 HW Stack Overflow P:$0A Misaligned Long Word Access P:$0C OnCE Step Counter P:$0E OnCE Breakpoint Unit 0 Reserved P:$12 OnCE Trace Buffer P:$14 OnCE Transmit Register Empty ...
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... SCI 0 Receiver Error P:$90 SCI 0 Receiver Full Reserved P:$94 ADC A Conversion Complete / End of Scan Reserved P:$98 ADC A Zero Crossing or Limit Error Reserved P:$9C Reload PWM A Reserved P:$A0 PWM A Fault P:$A2 SW Interrupt LP P:$A4 56F8323 Technical Data, Rev (Continued) Interrupt Function Freescale Semiconductor Preliminary ...
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... Flash Memory content, their state is maintained during power-down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual. These configuration parameters are located between $00_3FF7 and $00_3FFF. Freescale Semiconductor Preliminary Table 4-4 Data Memory Map Memory Allocation ...
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... Technical Data, Rev. 17 Data Memory FM_BASE + $14 Banked Registers Unbanked Registers FM_BASE + $00 8KB DATA_FLASH_START + $0000 Note: Data Flash is NOT available in the 56F8123 device. Sector Size Page Size bits 512 x 16 bits 256 x 16 bits 256 x 16 bits bits 256 x 16 bits Freescale Semiconductor Preliminary ...
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... OCR (bits) X:$FF FFFC OCLSR (8 bits) X:$FF FFFD OTXRXSR (8 bits) X:$FF FFFE OTX / ORX (32 bits) X:$FF FFFF OTX1 / ORX1 Freescale Semiconductor Preliminary Table 4-6 EOnCE Memory Map Reserved External Signal Control Register Reserved Breakpoint Unit [0] Counter Reserved Breakpoint 1 Unit [0] Mask Register ...
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... X:$00 F310 SIM X:$00 F350 LVI X:$00 F360 FM X:$00 F400 FC X:$00 F800 56F8323 Technical Data, Rev. 17 Table Number 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 Freescale Semiconductor Preliminary ...
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... TMRA2_CAP $22 TMRA2_LOAD $23 TMRA2_HOLD $24 TMRA2_CNTR $25 TMRA2_CTRL $26 TMRA2_SCR $27 TMRA2_CMPLD1 $28 Freescale Semiconductor Preliminary (TMRA_BASE = $00 F040) Address Offset Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 ...
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... Control Register $7 Status and Control Register $8 Comparator Load Register 1 $9 Comparator Load Register 2 $A Comparator Status and Control Register Reserved $10 Compare Register 1 $11 Compare Register 2 $12 Capture Register $13 Load Register 56F8323 Technical Data, Rev. 17 Register Description Register Description Freescale Semiconductor Preliminary ...
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... TMRC2_CTRL TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 TMRC2_COMSCR TMRC3_CMP1 TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR Freescale Semiconductor Preliminary (TMRC_BASE = $00 F0C0) Address Offset $14 Hold Register $15 Counter Register $16 Control Register $17 Status and Control Register $18 Comparator Load Register 1 $19 Comparator Load Register 2 $1A ...
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... Decoder Control Register $1 Filter Interval Register $2 Watchdog Time-out Register Position Difference Counter Register Position Difference Counter Hold Register $5 Revolution Counter Register $6 Revolution Hold Register $7 Upper Position Counter Register $8 Lower Position Counter Register 56F8323 Technical Data, Rev. 17 Register Description Register Description Freescale Semiconductor Preliminary ...
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... IRQP0 $11 IRQP1 $12 IRQP2 $13 IRQP3 $14 IRQP4 $15 IRQP5 $16 ICTL $1D Freescale Semiconductor Preliminary (DEC0_BASE = $00 F180) Address Offset $9 Upper Position Hold Register Lower Position Hold Register $B Upper Initialization Register $C Lower Initialization Register Input Monitor Register (ITCN_BASE = $00 F1A0) Address Offset Interrupt Priority Register 0 Interrupt Priority Register 1 ...
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... High Limit Register 0 $1A High Limit Register 1 $1B High Limit Register 2 $1C High Limit Register 3 $1D High Limit Register 4 $1E High Limit Register 5 $1F High Limit Register 6 $20 High Limit Register 7 56F8323 Technical Data, Rev. 17 Register Description Freescale Semiconductor Preliminary ...
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... Table 4-15 Serial Communication Interface 0 Registers Address Map Register Acronym SCI0_SCIBR SCI0_SCICR SCI0_SCISR SCI0_SCIDR Table 4-16 Serial Communication Interface 1 Registers Address Map Register Acronym SCI1_SCIBR SCI1_SCICR SCI1_SCISR SCI1_SCIDR Freescale Semiconductor Preliminary (ADCA_BASE = $00 F200) Address Offset $21 Offset Register 0 $22 Offset Register 1 $23 Offset Register 2 $24 Offset Register 3 ...
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... Data Receive Register Data Transmitter Register (COP_BASE = $00 F2C0) Address Offset Register Description Control Register Time-Out Register Counter Register (CLKGEN_BASE = $00 F2D0) Address Offset Register Description Control Register Divide-By Register Status Register Reserved Shutdown Register Oscillator Control Register 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... GPIOB_IENR $5 GPIOB_IPOLR $6 GPIOB_IPR $7 GPIOB_IESR $8 GPIOB_PPMODE $9 GPIOB_RAWDATA $A Freescale Semiconductor Preliminary (GPIOA_BASE = $00 F2E0) Address Offset Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register ...
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... I/O Short Address Location High Register I/O Short Address Location Low Register 56F8323 Technical Data, Rev. 17 Reset Value 0 x 007C 0 x 0000 0 x 0000 0 x 007F 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 007F — Register Description Freescale Semiconductor Preliminary ...
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... FMPROTB $11 FMUSTAT $13 FMCMD $14 FMOPT 0 $1A FMOPT 1 $1B FMOPT 2 $1C Freescale Semiconductor Preliminary (LVI_BASE = $00 F360) Address Offset Control Register Status Register (FM_BASE = $00 F400) Address Offset Register Description Clock Divider Register Module Control Register Reserved Security High Half Register Security Low Half Register ...
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... Message Buffer 0 Data Register $44 Message Buffer 0 Data Register $45 Message Buffer 0 Data Register $46 Message Buffer 0 Data Register Reserved $48 Message Buffer 1 Control / Status Register $49 Message Buffer 1 ID High Register $4A Message Buffer 1 ID Low Register 56F8323 Technical Data, Rev. 17 Register Description Freescale Semiconductor Preliminary ...
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... FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB5_CONTROL FCMB5_ID_HIGH FCMB5_ID_LOW FCMB5_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset $4B Message Buffer 1 Data Register $4C Message Buffer 1 Data Register $4D Message Buffer 1 Data Register $4E Message Buffer 1 Data Register Reserved $50 Message Buffer 2 Control / Status Register ...
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... Message Buffer 8 Data Register $86 Message Buffer 8 Data Register Reserved $88 Message Buffer 9 Control / Status Register $89 Message Buffer 9 ID High Register $8A Message Buffer 9 ID Low Register $8B Message Buffer 9 Data Register $8C Message Buffer 9 Data Register 56F8323 Technical Data, Rev. 17 Register Description Freescale Semiconductor Preliminary ...
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... FCMB11_DATA FCMB12_CONTROL FCMB12_ID_HIGH FCMB12_ID_LOW FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB13_CONTROL FCMB13_ID_HIGH FCMB13_ID_LOW FCMB13_DATA FCMB13_DATA FCMB13_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset $8D Message Buffer 9 Data Register $8E Message Buffer 9 Data Register Reserved $90 Message Buffer 10 Control / Status Register $91 Message Buffer 10 ID High Register $92 Message Buffer 10 ID Low Register ...
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... Message Buffer 15 Control / Status Register $B9 Message Buffer 15 ID High Register $BA Message Buffer 15 ID Low Register $BB Message Buffer 15 Data Register $BC Message Buffer 15 Data Register $BD Message Buffer 15 Data Register $BE Message Buffer 15 Data Register Reserved 56F8323 Technical Data, Rev. 17 Register Description Freescale Semiconductor Preliminary ...
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... The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition 1 SR[ Core status register bits indicating current interrupt mask within the core. Freescale Semiconductor Preliminary 4-3, Interrupt Vector Table Contents. 1 Permitted Exceptions SR[8] 0 Priorities ...
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... The core then fetches the instruction from the indicated vector adddress and not a JSR, the core starts its fast interrupt handling. 58 Current Interrupt Required Nested 1 Priority Level Exception Priority No Interrupt or SWILP Priorities Priority 0 Priorities Priority 1 Priorities 2, 3 Priorities Priority 3 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... This is because there is no clock available to detect the falling edge. A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB can wake it up. Freescale Semiconductor Preliminary any0 Level 0 82 -> ...
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... IRQ Pending Register 4 IRQ Pending Register 5 Reserved Interrupt Control Register 56F8323 Technical Data, Rev. 17 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18 5.6.19 5.6.20 5.6.21 5.6.22 5.6.23 5.6.30 Freescale Semiconductor Preliminary ...
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... IRQP0 W R $12 IRQP1 W R $13 IRQP2 W R $14 IRQP3 W R $15 IRQP4 $16 IRQP5 W Reserved R INT $1D ICTL W = Reserved Figure 5-2 ITCN Register Map Summary Freescale Semiconductor Preliminary BKPT_ U0 STPCNT IPL IPL FMCC IPL FMERR IPL LOCK IPL FCMSGBUF IPL 0 0 SPI1_XMIT SPI1_RCV IPL IPL ...
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... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $ Read Write RESET Figure 5-4 Interrupt Priority Register 1 (IPR1 STPCNT IPL 56F8323 Technical Data, Rev RX_REG IPL TX_REG IPL TRBUF IPL Freescale Semiconductor Preliminary ...
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... IRQ is priority level 2 • IRQ is priority level 3 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $ Read FMCBE IPL FMCC IPL Write RESET Figure 5-5 Interrupt Priority Register 2 (IPR2) Freescale Semiconductor Preliminary FMERR IPL LOCK IPL LVI IPL 56F8323 Technical Data, Rev. 17 Register Descriptions ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 64 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary ...
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... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.5 Interrupt Priority Register 4 (IPR4) Base + $ Read SPI0_RCV SPI1_XMIT IPL Write RESET Figure 5-7 Interrupt Priority Register 4 (IPR4 SPI1_RCV IPL IPL 56F8323 Technical Data, Rev GPIOA IPL GPIOB IPL GPIOC IPL Freescale Semiconductor Preliminary ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8323 Technical Data, Rev. 17 Register Descriptions 67 ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level SCI1_RCV SCI1_RERR IPL IPL 56F8323 Technical Data, Rev SCI1_TIDL SCI1_XMIT SPI0_XMIT IPL IPL IPL Freescale Semiconductor Preliminary 0 0 ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8323 Technical Data, Rev. 17 Register Descriptions 69 ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 56F8323 Technical Data, Rev DEC0_XIRQ DEC0_HIRQ IPL IPL Freescale Semiconductor Preliminary 0 0 ...
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... Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level SCI0_TIDL SCI0_XMIT IPL IPL 56F8323 Technical Data, Rev TMRA3 IPL TMRA2 IPL TMRA1 IPL IPL Freescale Semiconductor 0 0 Preliminary ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8323 Technical Data, Rev. 17 Register Descriptions 73 ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level PWMA_RL ADCA_ZC IPL IPL 56F8323 Technical Data, Rev ADCA_CC IPL Freescale Semiconductor Preliminary ...
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... Vector Base Address Register (VBA) Base + $ Read Write RESET Figure 5-13 Vector Base Address Register (VBA) 5.6.11.1 Reserved—Bits 15–13 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary VECTOR BASE ADDRESS 56F8323 Technical Data, Rev. 17 Register Descriptions 6 ...
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... The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 76 Part 5.3 4- FAST INTERRUPT 0 VECTOR ADDRESS LOW 56F8323 Technical Data, Rev. 17 for details FAST INTERRUPT Freescale Semiconductor Preliminary ...
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... Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table Freescale Semiconductor Preliminary ...
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... This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number FAST INTERRUPT 1 VECTOR ADDRESS LOW PENDING [16: 56F8323 Technical Data, Rev FAST INTERRUPT 1 VECTOR ADDRESS HIGH Freescale Semiconductor Preliminary ...
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... This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number 5.6.21 IRQ Pending 3 Register (IRQP3) Base + $ Read Write RESET Figure 5-23 IRQ Pending 3 Register (IRQP3) Freescale Semiconductor Preliminary PENDING [32:17 ...
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... This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number PENDING [80:65 56F8323 Technical Data, Rev PEND Freescale Semiconductor Preliminary ING [81] 1 ...
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... This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. Freescale Semiconductor Preliminary ...
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... IRQs with fixed priorities • Illegal Instruction • SW Interrupt 3 • HW Stack Overflow • Misaligned Long Word Access • SW Interrupt 2 • SW Interrupt 1 • SW Interrupt 0 • SW Interrupt LP These interrupts are enabled at their fixed priority levels. 82 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... Controls reset sequencing after reset • Software-initiated reset • Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control • System Control Register • Registers for software access to the JTAG ID of the chip Freescale Semiconductor Preliminary 56F8323 Technical Data, Rev. 17 Introduction 83 ...
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... Peripheral User Manual. Note: The OMR is not a Memory Map register directly accessible in code through the acronym OMR R/W R Figure 6-1 OMR 56F8323 Technical Data, Rev R/W R/W R/W R/W R Part 4.2 and Part 7 for detailed Freescale Semiconductor 0 MA R/W 0 Preliminary ...
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... SIM_PUDR Base + $A SIM_CLKOSR Base + $B SIM_GPS Base + $C SIM_PCE Base + $D SIM_ISALH Base + $E SIM_ISALL Freescale Semiconductor Preliminary Table 6-1 SIM Registers (SIM_BASE = $00F350) Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID ...
Page 86
... ADCA CAN DEC0 TMRC ISAL[21: 56F8323 Technical Data, Rev ONCE SW STOP_ EBL0 RST DISABLE DISABLE SWR COPR EXTR POR JTAG CLK CLKOSEL DIS TMRA SCI1 SCI0 SPI1 SPI0 ISAL[23:22 ONCE SW STOP_ EBL0 RST DISABLE DISABLE Freescale Semiconductor 0 WAIT_ PWMA 0 WAIT_ 0 Preliminary ...
Page 87
... When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST bit in the SIM CONTROL register). This bit will be cleared by any hardware reset or by software. Writing this bit position will set the bit, while writing the bit will clear it. Freescale Semiconductor Preliminary 12 ...
Page 88
... COP reset). 6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F4 FIELD 56F8323 Technical Data, Rev Freescale Semiconductor Preliminary 0 0 ...
Page 89
... Write RESET Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR) 6.5.6.1 Reserved—Bits 15–12 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.2 RESET—Bit 11 This bit controls the pull-up resistors on the RESET pin. Freescale Semiconductor Preliminary ...
Page 90
... Peripheral output function of GPIOB[7] is defined to be the oscillator clock (MSTR_OSC, see Figure 3-4) 6.5.7.3 PHASEB0 (PHSB)—Bit 8 • Peripheral output function of GPIOB[6] is defined to be PHASEB0 • Peripheral output function of GPIOB[6] is defined to be SYS_CLK2 PHSA PHSB INDEX HOME 56F8323 Technical Data, Rev CLK CLKOSEL DIS Freescale Semiconductor Preliminary 0 ...
Page 91
... The default peripherals are SPI 0, Quad Timer C, and PWMA. Note: PWM is NOT available in the 56F8123 device. As shown in Figure 6-10, the GPIO has the final control over the pin function. SIM_GPS simply decides which peripheral will be routed to the I/O. Freescale Semiconductor Preliminary 56F8323 Technical Data, Rev. 17 Register Descriptions Figure 3-4) ...
Page 92
... This bit selects the alternate function for GPIOC5. • TC1 (default) • RXD0 6.5.8.4 GPIOB1 (B1)—Bit 5 This bit selects the alternate function for GPIOB1. • MISO0 (default) • RXD1 92 GPIOX_PER Register GPIO Controlled SIM_GPS Register 56F8323 Technical Data, Rev I/O Pad Control Freescale Semiconductor Preliminary ...
Page 93
... The clocks can be individually controlled for each peripheral on the chip. Base + $ Read ADCA Write RESET Figure 6-12 Peripheral Clock Enable Register (SIM_PCE) 6.5.9.1 Reserved—Bits 15–14 This bit field is reserved or not implemented read as 1 and cannot be modified by writing. Freescale Semiconductor Preliminary CAN DEC0 TMRC ...
Page 94
... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.10 Serial Communications Interface 1 Enable (SCI1)—Bit 5 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 94 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
Page 95
... If this register is set ot something other than the top of memory (EOnCE register space) and the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected. Freescale Semiconductor Preliminary 56F8323 Technical Data, Rev. 17 Register Descriptions ...
Page 96
... This field represents the upper two address bits of the “hard coded” I/O short address. Base + $ Read Write RESET Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL) 96 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction ISAL[21: 56F8323 Technical Data, Rev. 17 Instruction Portion ISAL[23:22 Freescale Semiconductor Preliminary ...
Page 97
... All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK = 60MHz. Refer to the PCE register in frequency, which can be controlled through the OCCS. Freescale Semiconductor Preliminary Peripheral Clocks Active Device is fully functional ...
Page 98
... After completion of the described reset sequence, application code will begin execution. Resets may be asserted asynchronously, but are always released internally on a rising edge of the system clock D-FLOP D-FLOP C R Note: Wait disable Reset circuit is similar 56F8323 Technical Data, Rev. 17 56800E STOP_DIS Part 6.5.1. This procedure Freescale Semiconductor Preliminary ...
Page 99
... Proper implementation of Flash security requires that no access to the EOnCE port is provided when security is enabled. The 56800E core has an input which disables reading of internal memory via the JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the FM security bytes. Freescale Semiconductor Preliminary 56F8323 Technical Data, Rev. 17 Operation with Security Enabled ...
Page 100
... SYS_CLK 2 FMCLKDIV JTAG FMERASE Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. 100 Figure 7-1. FM_CLKDIV[6] will map to the Flash Memory input clock 7 FMCLKD 7 56F8323 Technical Data, Rev. 17 DIVIDER 7 Freescale Semiconductor Preliminary ...
Page 101
... Flash with the original code, but to modify the security bytes. To insure that a customer does not inadvertently lock himself out of the device during programming recommended that he program the backdoor access key first, his application code second and the security bytes within the FM configuration field last. Freescale Semiconductor Preliminary ( ) ...
Page 102
... Peripheral Function SPI 1 SPI 0, SCI 1, TMRA XTAL, EXTAL, TMRC, SCI 0 56F8323 Technical Data, Rev. 17 Reset Function PWM SPI 0, DEC 0 XTAL, EXTAL, CAN, TMRC Reset Function Must be reconfigured SPI 0; other pins must be reconfigured XTAL, EXTAL, TMRC; other pins must be reconfigured Freescale Semiconductor Preliminary ...
Page 103
... MISO0 / RXD1 GPIOB2 MOSI0 GPIOB3 SCLK0 GPIOB4 HOME0 / TA3 GPIOB5 INDEX0 / TA2 GPIOB6 PHASEB0 / TA1 Freescale Semiconductor Preliminary Package Pin 3 PWM is NOT available in 56F8123 4 PWM is NOT available in 56F8123 7 SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis PWM is NOT available in 56F8123 ...
Page 104
... SIM register SIM_GPS is used to select between Timer C and SCI0 on a pin-by-pin basis 1 SIM register SIM_GPS is used to select between Timer C and SCI0 on a pin-by-pin basis 4-21 through 56F8323 Technical Data, Rev. 17 Notes 4-23 define the actual reset values Freescale Semiconductor Preliminary ...
Page 105
... However, normal precautions are advised to avoid application maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Freescale Semiconductor Preliminary are stress ratings only, and functional operation at the maximum CAUTION of any voltages higher 56F8323 Technical Data, Rev ...
Page 106
... OUTOD drain mode STG T STG 56F8323 Technical Data, Rev. 17 Min Max Unit - 0.3 4 0.3 4 0.3 4 0.3 3.0 V -0.3 6.0 V -0.3 4.0 V -0.3 4 6.0 -0.3 6.0 V -40 125 °C -40 105 °C -40 150 °C -40 125 °C -55 150 °C -55 150 °C Freescale Semiconductor Preliminary ...
Page 107
... Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. See Part 12.1 for more details on thermal design considerations Junction temperature TA = Ambient temperature Freescale Semiconductor Preliminary Min 2000 200 500 Table 10-3 Thermal Characteristics ...
Page 108
... V +0.3 DDA DDA 2 — V +0.3 DDA -0.3 — 0.8 — — -4 — — -12 — — 4 — — 12 -40 — 125 -40 — 105 10,000 — — Cycles 10,000 — — Cycles 15 — — Freescale Semiconductor Preliminary Unit MHz °C °C Years ...
Page 109
... HYS Hysteresis C Input Capacitance INC (EXTAL/XTAL) C Output Capacitance OUTC (EXTAL/XTAL) C Input Capacitance IN C Output Capacitance OUT See Pin Groups in Table 10-1 Freescale Semiconductor Preliminary Notes Min Typ 2.4 — — — Pin Groups — 0 Pin Group Pin Group 8 — 0 Pin Group 7 — ...
Page 110
... Relaxation oscillator is off 0μA 145μA • All peripheral clocks are off • ADC powered off • PLL powered off 56F8323 Technical Data, Rev. 17 Typ Max Units — — V 1.8 1.9 V 2.14 — V 2.7 — V μA 110 130 Test Conditions Freescale Semiconductor Preliminary ...
Page 111
... The output voltage can be measured directly on the V pins. The specifications for this regulator are shown in Characteristic Unloaded Output Voltage (0mA Load) Loaded Output Voltage (200mA load) Line Regulation @ 250mA load (V 33 ranges from 3.0V to 3.6V) DD Freescale Semiconductor Preliminary DD_ADC DD_OSC_PLL DD_IO 13μA 25mA 2.5mA 13μ ...
Page 112
... DDA_ADC 56F8323 Technical Data, Rev. 17 Typical Max Unit — 700 mA 5 μ — 30 minutes Typical Max Unit 0 0. — 200 ps — 175 ps 1 μA 100 150 Max Unit — mV/°C 28 °C 128 °C 153 °C — V 3.6 V Freescale Semiconductor Preliminary ...
Page 113
... Active state, when a bus or signal is driven, and enters a low impedance state • Tri-stated, when a bus or signal is placed in a high impedance state • Data Valid state, when a signal level has reached V • Data Invalid state, when a signal level is in transition between V Freescale Semiconductor Preliminary Symbol Min I — DD-OFF I — ...
Page 114
... PW t — rise t — fall 56F8323 Technical Data, Rev. 17 Data3 Valid Data3 Data Active Typ Max Unit μs — — — — ms — — Typ Max Unit — 120 MHz — 80 MHz — — ns — — Freescale Semiconductor Preliminary ...
Page 115
... Crystal Oscillator Parameters Table 10-15 Crystal Oscillator Parameters Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal Min-Max Period Variation Resonator Peak-to-Peak Jitter Freescale Semiconductor Preliminary t PW – Figure 10-3 External Clock Timing Table 10-14 PLL Timing ...
Page 116
... BIASH I — 80 BIASL I — Min Typ — 8 — — 82 — — 41 — — +/- 1.78 +2 /-3 — — 500 — — 4 56F8323 Technical Data, Rev. 17 Typ Max Unit 300 ps μA 290 μA 110 μA 1 Max Units MHz μs Freescale Semiconductor Preliminary ...
Page 117
... In the formulas clock cycle. For an operating frequency of 60MHz 16.67ns. At 8MHz (used during Reset and Stop modes 125ns. 2. Parameters listed are guaranteed by design. 3. The interrupt instruction fetch is visible on the pins only in Mode 3. Freescale Semiconductor Preliminary Reset, Stop, Wait, Mode Select, and Interrupt Timing Typical Response ...
Page 118
... IRQA PAB Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing 118 IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I 56F8323 Technical Data, Rev RDA First Fetch First Instruction Fetch Not IRQA Interrupt Vector Freescale Semiconductor Preliminary ...
Page 119
... Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. Freescale Semiconductor Preliminary 1 Table 10-18 SPI Timing Symbol Min Max ELD — 25 ...
Page 120
... SS is held High on master MSB in Bits 14– Master MSB out Bits 14– held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8323 Technical Data, Rev LSB in (ref Master LSB out LSB in (ref Master LSB out t R Freescale Semiconductor Preliminary ...
Page 121
... SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-11 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output) MOSI (Input) Figure 10-12 SPI Slave Timing (CPHA = 1) Freescale Semiconductor Preliminary ELD Slave MSB out Bits 14– ...
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... P P OUTHL OUT Figure 10-13 Timer Timing Symbol Min 56F8323 Technical Data, Rev Max Unit See Figure — ns 10-13 — ns 10-13 — ns 10-13 — ns 10-13 P INHL P OUTHL 1, 2 Max Unit See Figure — ns 10-14 — ns 10-14 — ns 10-14 Freescale Semiconductor Preliminary ...
Page 123
... The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. RXD SCI receive data pin (Input) TXD SCI receive data pin (Input) Freescale Semiconductor Preliminary ...
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... Symbol Min f DC SYS_CLK SYS_CLK — — TRST 56F8323 Technical Data, Rev Max Unit See Figure 1 Mbps — μs — 10-17 Max Unit See Figure MHz 10-18 MHz 10-18 — ns 10-18 — ns 10-19 — ns 10- 10- 10-19 — ns 10-20 Freescale Semiconductor Preliminary ...
Page 125
... – Figure 10-18 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-19 Test Access Port Timing Diagram TRST (Input) Freescale Semiconductor Preliminary 1 )/ Input Data Valid TRST Figure 10-20 TRST Timing Diagram 56F8323 Technical Data, Rev ...
Page 126
... LSB +/- 0.7 < LSB — 5 MHz — REFH cycles AIC — — t cycles AIC 1 — t cycles AIC 5 — pF — — 1 — — mA μ +/- .004 +/- .01 — +/- 26 +/- 32 mV — LSBs — — -2.8 — — -60 — — V REFLO 64.6 — db Freescale Semiconductor Preliminary ...
Page 127
... ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible. 6. Absolute error includes the effects of both gain error and offset error. 7. Please see the 56F8300 Peripheral User’s Manual for additional information on ADC calibration. 8. ENOB = (SINAD - 1.76)/6.02 Freescale Semiconductor Preliminary Symbol Min SINAD — ...
Page 128
... Although not guaranteed believed that calibration will produce results similar to those shown above for any population of parts, including those which represent processing and temperature extremes. 128 = 0.60V and 2.70V in 56F8323 Technical Data, Rev. 17 was in Freescale Semiconductor Preliminary ...
Page 129
... These sources operate independently of processor state or operating frequency. B, the internal [state-dependent component], reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs. Freescale Semiconductor Preliminary )/2, while the other charges to the analog input voltage. When the ...
Page 130
... In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. 130 2 *F CMOS power dissipation corresponding to the Intercept 1.15mW Table 10-25 provides coefficients for calculating power dissipated 56F8323 Technical Data, Rev *F, although simulations on two Slope 1.3 0.11mW / pF 0.11mW / pF Freescale Semiconductor Preliminary ...
Page 131
... PWMA5 V SS IRQA FAULTA0 FAULTA1 FAULTA2 ISA0 Figure 11-1 Top View, 56F8323 64-Pin LQFP Package Freescale Semiconductor Preliminary Figure 11-1 shows the package outline for the 64-pin LQFP, ORIENTATION MARK 17 56F8323 Technical Data, Rev. 17 56F8323 Package and Pin-Out Information Table 11-1 ...
Page 132
... V DDA_OSC_PLL ANA1 43 V CAP ANA2 44 V ANA3 45 OCR_DIS ANA4 46 EXTAL ANA5 47 XTAL ANA6 48 V DD_IO 56F8323 Technical Data, Rev. 17 Pin No. Signal Name 49 HOME0 50 INDEX0 51 PHASEB0 52 PHASEA0 53 TCK 54 TMS 55 TDI 56 TDO CAP 58 TRST DD_IO CAN_RX 62 CAN_TX 63 TC3 64 TC1 Freescale Semiconductor Preliminary ...
Page 133
... SCLK1 V SS IRQA GPIOA6 GPIOA7 GPIOA8 GPIOA9 Figure 11-2 Top View, 56F8123 64-Pin LQFP Package Freescale Semiconductor Preliminary Figure 11-1 shows the package outline for the 64-pin LQFP, ORIENTATION MARK 17 56F8323 Technical Data, Rev. 17 56F8123 Package and Pin-Out Information Table 11-1 ...
Page 134
... V DDA_OSC_PLL ANA1 43 V CAP ANA2 44 V ANA3 45 OCR_DIS ANA4 46 EXTAL ANA5 47 XTAL ANA6 48 V DD_IO 56F8323 Technical Data, Rev. 17 Pin No. Signal Name 49 TA3 50 TA2 51 TA1 52 TA0 53 TCK 54 TMS 55 TDI 56 TDO CAP 58 TRST DD_IO GPIOC2 62 GPIOC3 63 TC3 64 TC1 Freescale Semiconductor Preliminary ...
Page 135
... H A VIEW D1/2 D SEATING C PLANE 60X VIEW Y Figure 11-3 64-pin LQFP Mechanical Information Please see www.freescale.com for the most current case outline. Freescale Semiconductor Preliminary 4X 16 TIPS 0 E1 VIEW AA BASE METAL PLATING b 0. SECTION AB-AB ° ...
Page 136
... Thermal characterization parameter ( Power dissipation in package (W) D 136 , can be obtained from the equation C/W) . For instance, the user can change the size of the heat θCA ) can be used to determine the junction temperature with C)/W 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
Page 137
... Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V • Bypass the V and capacitor such as a tantalum capacitor Freescale Semiconductor Preliminary CAUTION of any voltages (GND) pin /V Ceramic and tantalum capacitors tend to provide better DDA SSA ...
Page 138
... REG OCS ROSC 138 , V REF DDA pins. bus CAP REG CORE V SS Figure 12-1 Power Management 56F8323 Technical Data, Rev. 17 and V pins SSA pin and cannot DDA_OSC_PLL DD_CORE V DDA_ADC V REFH V REFP I/O V ADC REFMID V REFN V REFLO V SSA_ADC Freescale Semiconductor Preliminary voltage ...
Page 139
... Technical Data, Rev. 17 Power Distribution and I/O Ring Implementation Temperature Order Number (MHz) Range 60 -40° 105° C MC56F8323VFB60 60 -40° 125° C MC56F8323MFB60 40 -40° 105° C MC56F8123VFB 60 -40° 105° C MC56F8323VFBE* 60 -40° 125° C MC56F8323MFBE* 40 -40° 105° C ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...