MC68HC711E9CFU2 Freescale Semiconductor, MC68HC711E9CFU2 Datasheet - Page 45

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MC68HC711E9CFU2

Manufacturer Part Number
MC68HC711E9CFU2
Description
IC MCU 12K OTP 2MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E9CFU2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
NOSEC — Security Disable Bit
NOCOP — COP System Disable Bit
ROMON — ROM/EPROM/OTPROM Enable Bit
EEON — EEPROM Enable Bit
2.3.3.2 RAM and I/O Mapping Register
The internal registers used to control the operation of the MCU can be relocated on 4-Kbyte boundaries
within the memory space with the use of the RAM and I/O mapping register (INIT). This 8-bit
special-purpose register can change the default locations of the RAM and control registers within the
MCU memory map. It can be written only once within the first 64 E-clock cycles after a reset in normal
modes, and then it becomes a read-only register.
RAM[3:0] — RAM Map Position Bits
REG[3:0] — 64-Byte Register Block Position
Freescale Semiconductor
NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If the
security mask option is omitted NOSEC always reads 1. The enhanced security feature is available in
the MC68S711E9 MCU. The enhancement to the standard security feature protects the EPROM as
well as RAM and EEPROM.
Refer to
When this bit is 0, the ROM or EPROM is disabled and that memory space becomes externally
addressed. In single-chip mode, ROMON is forced to 1 to enable ROM/EPROM regardless of the state
of the ROMON bit.
When this bit is 0, the EEPROM is disabled and that memory space becomes externally addressed.
These four bits, which specify the upper hexadecimal digit of the RAM address, control position of RAM
in the memory map. RAM can be positioned at the beginning of any 4-Kbyte page in the memory map.
It is initialized to address $0000 out of reset. Refer to
These four bits specify the upper hexadecimal digit of the address for the 64-byte block of internal
registers. The register block, positioned at the beginning of any 4-Kbyte page in the memory map, is
initialized to address $1000 out of reset. Refer to
0 = Security enabled
1 = Security disabled
1 = COP disabled
0 = COP enabled
0 = ROM disabled from the memory map
1 = ROM present in the memory map
0 = EEPROM removed from the memory map
1 = EEPROM present in the memory map
Chapter 5 Resets and
Address: $103D
Reset:
Read:
Write:
RAM3
Bit 7
0
Figure 2-12. RAM and I/O Mapping Register (INIT)
RAM2
Interrupts.
6
0
M68HC11E Family Data Sheet, Rev. 5.1
RAM1
5
0
RAM0
4
0
Table
Table
2-5.
REG3
3
0
2-4.
REG2
2
0
REG1
1
0
REG0
Bit 0
1
Memory Map
45

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