MC68HC711K4CFN4 Freescale Semiconductor, MC68HC711K4CFN4 Datasheet - Page 123

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MC68HC711K4CFN4

Manufacturer Part Number
MC68HC711K4CFN4
Description
IC MCU 24K OTP 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711K4CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
62
Program Memory Size
24KB (24K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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5.7 Reset and Interrupt Processing
M68HC11K Family
MOTOROLA
NOTE:
Address: $003C
Any single maskable interrupt can be given priority over other maskable
interrupts by writing the appropriate value to the PSEL bits in the HPRIO
register (see
still subject to global masking by the I bit in the CCR or by any associated
local bits. Interrupt vectors are not affected by priority assignment.
To avoid race conditions, HPRIO is designed so that bits PSEL[4:0] can
be written only while the I-bit is set (interrupts are inhibited).
PSEL[4:0] — Priority Select Bits
This section presents flow diagrams of the reset and interrupt processes.
Figure 5-8
detection relates to normal opcode fetches.
of a block in
shows the resolution of interrupt sources within the SCI subsystem.
Reset:
Read:
Write:
These bits select one interrupt source to have the highest priority, as
explained in
Freescale Semiconductor, Inc.
For More Information On This Product,
RBOOT
Bit 7
0
illustrates how the CPU begins from a reset and how interrupt
Go to: www.freescale.com
Figure 5-7. Highest Priority I-Bit Interrupt
Figure 5-8
Figure
Resets and Interrupts
and Miscellaneous Register (HPRIO)
Table
SMOD
6
0
5-7). An interrupt that is assigned highest priority is
5-7.
and illustrates interrupt priorities.
MDA
5
0
PSEL4
4
0
PSEL3
3
0
Figure 5-9
Reset and Interrupt Processing
PSEL2
2
1
Resets and Interrupts
is an expansion
PSEL1
Figure 5-10
1
1
Technical Data
PSEL0
Bit 0
0
123

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