MC68HC711K4CFN4 Freescale Semiconductor, MC68HC711K4CFN4 Datasheet - Page 201

• Manufacturer Part Number: MC68HC711K4CFN4
• Description: IC MCU 24K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.6.6 Timer Compare Force Register
M68HC11K Family
MOTOROLA
Address: $000B
The CFORC register allows forced early compares. Writing a 1 to any bit
of FOC[1:5] forces the programmed pin actions for the corresponding
OC channel to occur at the next timer count transition after the write to
CFORC. The action taken as a result of a forced compare is identical to
the action taken when a match between the OCx register and the
free-running counter occurs, except that the corresponding interrupt and
status flag bits are not set.
CFORC should not be applied to an output compare function that is
programmed to toggle its output on a successful compare because a
normal compare that occurs immediately before or after the force can
result in an undesirable operation.
FOC[1:5] — Force Output Comparison Bits
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = No action taken
1 = Output x action occurs at the next timer count transition
Figure 9-18. Timer Compare Force Register (CFORC)
OMx
FOC1
Bit 7
0
0
1
1
0
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Table 9-4. Timer Output Compare Actions
FOC2
OLx
Timing System
6
0
0
1
0
1
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line to 0
Set OCx output line to 1
FOC3
5
0
Action Taken on Successful Compare
FOC4
4
0
FOC5
3
0
2
0
0
Output Compare (OC)
1
0
0
Timing System
Technical Data
Bit 0
0
0
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