MC68HC711K4CFN4 Freescale Semiconductor, MC68HC711K4CFN4 Datasheet - Page 207

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MC68HC711K4CFN4

Manufacturer Part Number
MC68HC711K4CFN4
Description
IC MCU 24K OTP 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711K4CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
62
Program Memory Size
24KB (24K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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9.7.4 Timer Interrupt Mask 2 Register
M68HC11K Family
MOTOROLA
Address: $0024
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2.
PAOVF — Pulse Accumulator Overflow Flag
PAOVI — Interrupt Enable Bit
PAIF — Pulse Accumulator Input Edge Flag
PAII — Interrupt Enable Bit
Reset:
Read:
Write:
The PAOVF status bit is set each time the pulse accumulator count
rolls over from $FF to $00.
If PAOVI is set, an interrupt request is also generated. If PAOVI is
cleared, pulse accumulator overflow interrupts are inhibited, and
PAOVF must be polled by user software to determine when an
overflow has occurred. In either case, software must clear PAOVF by
writing a 1 to bit 5 in the TFLG2 register.
The PAIF status bit is automatically set each time a selected edge is
detected at the PA7 pin.
If PAII is set, an interrupt request is also generated. If PAII is cleared,
pulse accumulator input interrupts are inhibited, and PAIF must be
polled by user software to determine when an input edge has been
detected. In either case, software must clear PAIF by writing a 1 to
bit 5 in the TFLG2 register.
Freescale Semiconductor, Inc.
For More Information On This Product,
Bit 7
TOI
0
Figure 9-25. Timer Interrupt Mask 2 (TMSK2)
Go to: www.freescale.com
RTII
Timing System
6
0
PAOVI
5
0
PAII
4
0
3
0
0
2
0
0
Pulse Accumulator (PA)
PR1
1
0
Timing System
Technical Data
Bit 0
PR0
0
207

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