MC68HC711K4CFN4 Freescale Semiconductor, MC68HC711K4CFN4 Datasheet - Page 223

• Manufacturer Part Number: MC68HC711K4CFN4
• Description: IC MCU 24K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.3.1 Multiplexer
10.3.2 Analog Converter
10.3.3 Result Registers
M68HC11K Family
MOTOROLA
The multiplexer selects which of the eight analog inputs at port E will be
converted. There are also three internal reference levels which can be
multiplexed to the converter for system testing. Input selection is
controlled by the value of bits CD:CA in the A/D control register
(ADCTL).
The V
voltage. An input voltage equal to V
voltage equal to V
indication. For ratiometric conversions of this type, the source of
each analog input should use V
referenced to V
The conversion block contains a digital-to-analog capacitor (DAC) array,
a comparator, and a successive approximation register (SAR). When an
analog input is sampled for conversion, an analog switch connects the
input to the DAC array. This series of scaled capacitors retains the
sample for the duration of the conversion.
A conversion consists of a sequence of eight comparison operations.
Each comparison determines one bit of the result, starting with the most
significant bit (MSB). During each comparison, analog switches connect
different elements of the DAC array to the comparator. The output of the
comparator is stored in the next bit in the successive approximation
register. When a conversion sequence is complete, the contents of the
SAR are transferred to the appropriate result register.
The A/D conversion sequence begins one E-clock cycle after a write to
the analog-to-digital control/status register (ADCTL). Converter
operations are performed in sequences of four conversions each. Each
conversion result in a sequence is stored in one of the four result
registers, ADR[4:1]. The conversion complete flag (CCF) in the ADCTL
Freescale Semiconductor, Inc.
For More Information On This Product,
RH
and V
Analog-to-Digital (A/D) Converter
Go to: www.freescale.com
RL
RL
.
pins provide inputs for the A/D system reference
RH
converts to $FF (full scale), with no overflow
RH
as the supply voltage and be
RL
converts to $00 and an input
Analog-to-Digital (A/D) Converter
Functional Description
Technical Data
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