MC68HC711K4CFN4 Freescale Semiconductor, MC68HC711K4CFN4 Datasheet - Page 93

• Manufacturer Part Number: MC68HC711K4CFN4
• Description: IC MCU 24K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.8 EEPROM and the CONFIG Register
M68HC11K Family
MOTOROLA
This procedure programs one byte into EPROM. On entry, accumulator
A contains the byte of data to be programmed and X contains the target
EPROM address.
The 640-byte on-board EEPROM is enabled by the EEON bit in the
CONFIG register and located on a 4-K boundary determined by the
INIT2 register
programming voltage for the EEPROM, eliminating the need for an
external high-voltage supply.
When appropriate bits in the BPROT register are cleared, the PPROG
register controls programming and erasing the EEPROM. The PPROG
register can be read or written at any time, but logic enforces defined
programming and erasing sequences to prevent unintentional changes
to EEPROM data. When the EELAT bit in the PPROG register is cleared,
the EEPROM can be read as if it were a ROM.
The clock source driving the charge pump is software selectable. When
the clock select (CSEL) bit in the OPTION register is 0, the E clock is
used; when CSEL is 1, an on-chip resistor-capacitor (RC) oscillator is
used.
The EEPROM programming voltage power supply voltage to the
EEPROM array is not enabled until there has been a write to PPROG
with EELAT set and PGM cleared. This must be followed by a write to a
valid EEPROM location or to the CONFIG address, and then a write to
PPROG with both the EELAT and EPGM bits set. Any attempt to set
Freescale Semiconductor, Inc.
EPROG LDAB
For More Information On This Product,
Operating Modes and On-Chip Memory
STAB
STAA
LDAB
STAB
JSR
CLR
Go to: www.freescale.com
(4.6.3
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EEPROM). An internal charge pump supplies the
Set ELAT bit to enable EPROM latches.
(EPGM must be 0.)
Store data to EPROM address
Set EPGM bit with ELAT=1
to enable EPROM programming voltage
Delay 1-2 ms
Turn off programming voltage and set to
READ mode
Operating Modes and On-Chip Memory
EEPROM and the CONFIG Register
Technical Data
93