MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 136

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

External Interrupt Module (IRQ1)
15.4 IRQ Pin
A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
If the MODE bit is set, the IRQ1 pin is both falling-edge sensitive and low-level sensitive. With MODE set,
both of the following actions must occur to clear the IRQ latch:
The vector fetch or software clear and the return of the IRQ1 pin to logic 1 can occur in any order. The
interrupt request remains pending as long as the IRQ1 pin is at logic 0. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ1 pin is falling-edge sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected
by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
15.5 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ interrupt latch can be cleared during the
break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the
latches during the break state. (See
To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch
is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default
state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on
the IRQ latch.
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Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK
bit in the interrupt status and control register (ISCR). The ACK bit is useful in applications that poll
the IRQ1 pin and require software to clear the IRQ latch. Writing to the ACK bit can also prevent
spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ1
pin. A falling edge on IRQ that occurs after writing to the ACK bit latches another interrupt request.
If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address
at locations $FFFA and $FFFB.
Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at logic 0, the IRQ1 latch remains set.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
MC68HC908AZ32A Data Sheet, Rev. 2
7.7.3 SIM Break Flag Control Register
NOTE
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