MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 177

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

17.8 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates when the transmit data buffer
is ready to accept new data. Write to the SPI data register only when the SPTE bit is high.
shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has
CPHA:CPOL = 1:0).
For a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having
to time the write of its data between the transmissions. Also, if no new data is written to the data buffer,
the last value contained in the shift register will be the next data word transmitted.
Freescale Semiconductor
SPSCK (CPHA:CPOL = 1:0)
WRITE TO SPDR
READ SPSCR
READ SPDR
1
2
3
4
5
6
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
SPRF
CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET.
SPTE
MOSI
1
Figure 17-10. SPRF/SPTE CPU Interrupt Timing
MC68HC908AZ32A Data Sheet, Rev. 2
MSB BIT
BYTE 1
2
6
BIT
5
3
BIT
4
BIT
3
BIT
2
BIT
1
10
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
7
8
9
LSB MSB BIT
5
4
CPU READS SPDR, CLEARING SPRF BIT.
CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
BYTE 2
6
6
7
BIT
5
8
BIT
4
BIT
3
BIT
2
Queuing Transmission Data
BIT
1
LSB MSB BIT
10
9
BYTE 3
11
6
12
Figure 17-10
BIT
5
BIT
4
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