MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 215

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TOF — TIMB Overflow Flag Bit
TOIE — TIMB Overflow Interrupt Enable Bit
TSTOP — TIMB Stop Bit
TRST — TIMB Reset Bit
Freescale Semiconductor
This read/write flag is set when the TIMB counter resets to $0000 after reaching the modulo value
programmed in the TIMB counter modulo registers. Clear TOF by reading the TIMB status and control
register when TOF is set and then writing a logic 0 to TOF. If another TIMB overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1
to TOF has no effect.
This read/write bit enables TIMB overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
This read/write bit stops the TIMB counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIMB counter until software clears the TSTOP bit.
Setting this write-only bit resets the TIMB counter and the TIMB prescaler. Setting TRST has no effect
on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMB
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = TIMB counter has reached modulo value
0 = TIMB counter has not reached modulo value
1 = TIMB overflow interrupts enabled
0 = TIMB overflow interrupts disabled
1 = TIMB counter stopped
0 = TIMB counter active
1 = Prescaler and TIMB counter cleared
0 = No effect
Address:
Do not set the TSTOP bit before entering wait mode if the TIMA is required
to exit wait mode. Also, when the TSTOP bit is set and input capture mode
is enabled, input captures are inhibited until TSTOP is cleared.
When using TSTOP to stop the timer counter, see if any timer flags are set.
If a timer flag is set, it must be cleared by clearing TSTOP, then clearing the
flag, then setting TSTOP again.
Setting the TSTOP and TRST bits simultaneously stops the TIMB counter
at a value of $0000.
Reset:
Read:
Write:
Figure 19-4. TIMB Status and Control Register (TBSC)
$0040
Bit 7
TOF
R
0
0
= Reserved
TOIE
6
0
MC68HC908AZ32A Data Sheet, Rev. 2
TSTOP
5
1
NOTE
NOTE
TRST
4
0
0
R
3
0
0
PS2
2
0
PS1
1
0
Bit 0
PS0
0
I/O Registers
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