MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 246

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

I/O Ports
23.3 Port B
Port B is an 8-bit special function port that shares all of its pins with the analog-to-digital converter.
23.3.1 Port B Data Register
The port B data register contains a data latch for each of the eight port B pins.
PTB[7:0] — Port B Data Bits
ATD[7:0] — ADC Channels
23.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to
a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer.
DDRB[7:0] — Data Direction Register B Bits
246
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
PTB7–PTB0 are eight of the analog-to-digital converter channels. The ADC channel select bits,
CH[4:0], determine whether the PTB7–PTB0 pins are ADC channels or general-purpose I/O pins. If an
ADC channel is selected and a read of this corresponding bit in the port B data register occurs, the
data will be 0 if the data direction for this bit is programmed as an input. Otherwise, the data will reflect
the value in the data latch. (See
register B (DDRB) does not affect the data direction of port B pins that are being used by the ADC.
However, the DDRB bits always determine whether reading port B returns to the states of the latches
or logic 0.
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Functions:
Address:
Alternate
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
DDRB7
$0001
$0005
PTB7
ATD7
Bit 7
Bit 7
0
Figure 23-6. Data Direction Register B (DDRB)
Figure 23-5. Port B Data Register (PTB)
DDRB6
PTB6
ATD6
6
6
0
Chapter 21 Analog-To-Digital Converter
MC68HC908AZ32A Data Sheet, Rev. 2
DDRB5
PTB5
ATD5
5
5
0
DDRB4
Unaffected by Reset
PTB4
ATD4
4
4
0
DDRB3
PTB3
ATD3
3
3
0
DDRB2
ATD2
PTB2
2
2
0
(ADC-15)). Data direction
DDRB1
ATD1
PTB1
1
1
0
Freescale Semiconductor
DDRB0
ATD0
PTB0
Bit 0
Bit 0
0