MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 265

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Above behavior cannot be achieved with a single transmit buffer. That buffer must be reloaded right after
the previous message has been sent. This loading process lasts a definite amount of time and has to be
completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages.
Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to
the transmit interrupt.
A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message
being sent and as such reduces the reactiveness requirements on the CPU. Problems may arise if the
sending of a message would be finished just while the CPU re-loads the second buffer. In that case, no
buffer would then be ready for transmission and the bus would be released.
At least three transmit buffers are required to meet the first of the above requirements under all
circumstances. The MSCAN08 has three transmit buffers.
The second requirement calls for some sort of internal prioritisation which the MSCAN08 implements with
the “local priority” concept described in
24.4.2 Receive Structures
The received messages are stored in a 2-stage input first in first out (FIFO). The two message buffers are
mapped using a Ping Pong arrangement into a single memory area (see
background receive buffer (RxBG) is exclusively associated to the MSCAN08, the foreground receive
buffer (RxFG) is addressable by the CPU08. This scheme simplifies the handler software, because only
one address area is applicable for the receive process.
Both buffers have a size of 13 bytes to store the CAN control bits, the identifier (standard or extended),
and the data content (for details, see
The receiver full flag (RXF) in the MSCAN08 receiver flag register (CRFLG) (see
Receiver Flag Register
contains a correctly received message with matching identifier, this flag is set.
On reception, each message is checked to see if it passes the filter (for details see
Acceptance
RxFG
has to read the received message from RxFG and to reset the RXF flag to acknowledge the interrupt and
to release the foreground buffer. A new message which can follow immediately after the IFS field of the
CAN frame, is received into RxBG. The overwriting of the background buffer is independent of the
identifier filter function.
When the MSCAN08 module is transmitting, the MSCAN08 receives its own messages into the
background receive buffer, RxBG. It does NOT overwrite RxFG, generate a receive interrupt or
acknowledge its own messages on the CAN bus. The exception to this rule is in loop-back mode (see
24.13.2 MSCAN08 Module Control Register
all other incoming messages. The MSCAN08 receives its own transmitted messages in the event that it
loses arbitration. If arbitration is lost, the MSCAN08 must be prepared to become receiver.
An overrun condition occurs when both the foreground and the background receive message buffers are
filled with correctly received messages with accepted identifiers and another message is correctly
received from the bus with an accepted identifier. The latter message will be discarded and an error
1. Only if the RXF flag is not set.
2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also.
Freescale Semiconductor
(1)
, sets the RXF flag, and generates a receive interrupt to the CPU
Filter) and in parallel is written into RxBG. The MSCAN08 copies the content of RxBG into
(CRFLG)), signals the status of the foreground receive buffer. When the buffer
MC68HC908AZ32A Data Sheet, Rev. 2
24.12 Programmer’s Model of Message
24.4.2 Receive
1), where the MSCAN08 treats its own messages exactly like
Structures.
Figure
(2)
. The user’s receive handler
Storage).
24-2). While the
24.13.5 MSCAN08
24.5 Identifier
Message Storage
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